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T0501SA Datasheet(PDF) 2 Page - Chip Integration Technology Corporation

Part # T0501SA
Description  Ultra-Low Capacitance ESD Protection Device
PDF  7 Pages
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Manufacturer  CITC [Chip Integration Technology Corporation]
Direct Link  http://www.citcorp.com.tw/english/index.php
Logo CITC - Chip Integration Technology Corporation

T0501SA Datasheet(HTML) 2 Page - Chip Integration Technology Corporation

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Absolute Maximum Rating
Electrical Characteristics (T = 25 C)
Rating
Symbol
Value
Units
Peak Pulse Power (tp = 8/20μs)
Ppk
100
Watts
Peak Pulse Current (tp = 8/20
IPP
4.5
A
1
ESD per IEC 61000-4-2 (Air)
1
ESD per IEC 61000-4-2 (Contact)
VESD
±25
±22
kV
Operating Temperature
TJ
-55 to +125
°C
Storage Temperature
TSTG
-55 to +150
°C
Parameter
Symbol
Conditions
Minimum
Typical
Maximum
Units
Reverse Stand-Off Voltage
VRWM
5
V
Reverse Breakdown Voltage
VBR
I = 1mA
t
7
9
10
V
Reverse Leakage Current
IR
V
= 5V, T=25°C
RWM
0.005
0.100
μA
Clamping Voltage
VC
I
= 1A, tp = 8/20μs
PP
11
V
Clamping Voltage
VC
I
= 4A, tp = 8/20μs
PP
15
V
2, 3, 4
Dynamic Resistance
RD
tp = 100ns
0.90
Ohms
Junction Capacitance
C j
V
= 0V, f = 1MHz
R
0.25
0.4
pF
Notes
1) ESD gun return path connect
ed to ESD ground reference plane.
2) Transmission Line Pulse Test (TLP) Settings: tp= 100ns, tr= 0.
2ns,I
and V
averaging window: t1 = 70ns to t2= 90ns.
3) Dynamic resistance calculated from I
= 4A to I
= 16A
4) Guaranteed by design. No
t production tested
TLP
μs)
°
°C
TLP
TLP
TLP
Document ID : DS-22V02
Revised Date : 2016/08/29
Revision : C
Ultra-Low Capacitance ESD Protection Device
T0501SA
Chip Integration Technology Corporation



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