AD9600 datasheet(39/73 Pages) AD

39 / 73 page

AD9600

Rev. B | Page 38 of 72

SERIAL PORT INTERFACE (SPI)

The AD9600 SPI allows the user to configure the converter for

specific functions or operations through a structured register

space provided inside the ADC. This may provide the user

with additional flexibility and customization, depending on the

application. Addresses are accessed via the serial port and can

be written to or read from via the port. Memory is organized

into bytes that can be further divided into fields, which are docu-

mented in the Memory Map section. For detailed operational

information, see AN-877 Application Note, Interfacing to High

Speed ADCs via SPI.

CONFIGURATION USING THE SPI

There are three pins that define the SPI: SCLK, SDIO, and CSB

(see Table 19). The SCLK pin is used to synchronize the read

and write data presented from and to the ADC. The SDIO pin is

a dual-purpose pin that allows data to be sent to and read from

the internal ADC memory map registers. The CSB pin is an active-

low control that enables or disables the read and write cycles.

Table 19. Serial Port Interface Pins

Function

SCLK

Serial Clock. The serial shift clock input, which is used to

synchronize serial interface reads and writes.

SDIO

Serial Data Input/Output. A dual-purpose pin that

typically serves as an input or an output, depending on

the instruction being sent and the relative position in the

timing frame.

CSB

Chip Select Bar. An active-low control that gates the read

and write cycles.

The falling edge of the CSB in conjunction with the rising edge

of the SCLK determines the start of the framing. An example of

the serial timing and its definitions can be found in Figure 72

and Table 5.

Other modes involving the CSB are available. The CSB can be

held low indefinitely, which permanently enables the device;

this is called streaming. The CSB can stall high between bytes to

allow for additional external timing. When CSB is tied high, SPI

functions are placed in high impedance mode. This mode turns

on any secondary functions of the SPI pin.

During an instruction phase, a 16-bit instruction is transmitted.

Data follows the instruction phase, and its length is determined

by the W0 and W1 bits. W0 and W1 represent the number of

data bytes to transfer for either a read or a write. The value

represented by W1:W0 + 1 is the number of bytes to transfer.

All data is composed of 8-bit words. The first bit of the first

byte in a multibyte serial data transfer frame indicates whether

a read command or a write command is issued. This allows the

serial data input/output (SDIO) pin to change direction from an

input to an output.

In addition to word length, the instruction phase determines if

the serial frame is a read or write operation, allowing the serial

port to be used to both program the chip and read the contents

of the on-chip memory. If the instruction is a readback operation,

performing a readback causes the SDIO pin to change direction

from an input to an output at the appropriate point in the

serial frame.

Data can be sent in MSB-first mode or LSB-first mode. MSB-first

mode is the default on power-up and can be changed via the SPI

port configuration register (Address 0x00). For more information

about this and other features, see AN-877 Application Note,

Interfacing to High Speed ADCs via SPI.

HARDWARE INTERFACE

The pins described in Table 19 constitute the physical interface

between the user programming device and the serial port of the

AD9600. The SCLK pin and the CSB pin function as inputs

when using the SPI interface. The SDIO pin is bidirectional,

functioning as an input during write phases and as an output

during readback.

The SPI interface is flexible enough to be controlled by either

FPGAs or microcontrollers. One method for SPI configuration

is described in detail in AN-812 Application Note, Microcontroller-

Based Serial Port Interface (SPI) Boot Circuit.

The SPI port should not be active during periods when the full

dynamic performance of the converter is required. Because the

SCLK, CSB, and SDIO signals are typically asynchronous to the

ADC clock, noise from these signals can degrade converter

performance. If the on-board SPI bus is used for other devices, it

may be necessary to provide buffers between this bus and the

AD9600 to keep these signals from transitioning at the converter

inputs during critical sampling periods.

Some pins serve a dual function when the SPI interface is not

being used. When the pins are strapped to AVDD or ground

during device power-on, they are associated with a specific

function. The Theory of Operation section describes the

strappable functions supported on the AD9600.

AD9600 Datasheet(PDF) 39 Page - Analog Devices

AD9600 Datasheet(HTML) 39 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73

Datasheet Download

Link URL