AD9600 datasheet(16/73 Pages) AD

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AD9600

Rev. B | Page 15 of 72

DRVDD

DNC

(LSB) D0–

D0+

DCO–

DCO+

D1–

D1+

D2–

D2+

D3–

SCLK/DFS

SDIO/DCS

AVDD

VIN + B

VIN – B

RBIAS

CML

SENSE

VREF

VIN – A

VIN + A

AVDD

SMI SDFS

SMI SCLK/PDWN

SMI SDO/OEB

PIN 1

INDICATOR

AD9600

PARALLEL LVDS

TOP VIEW

(Not to Scale)

EXPOSED PADDLE, PIN 0

(BOTTOM OF PACKAGE)

NOTES

1. DNC = DO NOT CONNECT.

2. THE EXPOSED THERMAL PAD ON THE BOTTOM OF THE PACKAGE PROVIDES THE

ANALOG GROUND FOR THE PART. THIS EXPOSED PAD MUST BE CONNECTED TO

GROUND FOR PROPER OPERATION.

Figure 7. Interleaved Parallel LVDS Mode Pin Configuration (Top View)

Table 9. Interleaved Parallel LVDS Mode Pin Function Descriptions

Pin No.

Mnemonic

Type

Description

ADC Power Supplies

20, 64

DRGND

Ground

Digital Output Ground.

1, 21

DRVDD

Supply

Digital Output Driver Supply (1.8 V to 3.3 V).

24, 57

DVDD

Supply

Digital Power Supply (1.8 V Nominal).

36, 45, 46

AVDD

Supply

Analog Power Supply (1.8 V Nominal).

AGND

Ground

Analog Ground. Pin 0 is the exposed thermal pad on the bottom of the package.

ADC Inputs

VIN + A

Input

Differential Analog Input Pin (+) for Channel A.

VIN − A

Input

Differential Analog Input Pin (−) for Channel A.

VIN + B

Input

Differential Analog Input Pin (+) for Channel B.

VIN − B

Input

Differential Analog Input Pin (−) for Channel B.

VREF

I/O

Voltage Reference Input/Output.

SENSE

Input

Voltage Reference Mode Select (see Table 11 for details).

RBIAS

Input

External Reference Bias Resistor.

CML

Output

Common-Mode Level Bias Output for Analog Inputs.

CLK+

Input

ADC Master Clock True. The ADC clock can be driven using a single-ended CMOS

(see Figure 60 and Figure 61 for the recommended connection).

CLK−

Input

ADC Master Clock Complement. The ADC clock can be driven using a single-ended

CMOS (see Figure 60 and Figure 61 for the recommended connection).

AD9600 Datasheet(PDF) 16 Page - Analog Devices

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