AD9600 datasheet(11/73 Pages) AD

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AD9600

Rev. B | Page 10 of 72

TIMING CHARACTERISTICS

Table 5.

Parameter

Conditions

Min

Typ

Max

Unit

SYNC TIMING REQUIREMENTS

tSSYNC

Setup time between SYNC and the rising edge of CLK+

0.24

tHSYNC

Hold time between SYNC and the rising edge of CLK+

0.40

SPI TIMING REQUIREMENTS

tDS

Setup time between the data and the rising edge of SCLK

tDH

Hold time between the data and the rising edge of SCLK

tCLK

Period of the SCLK

Setup time between CSB and SCLK

Hold time between CSB and SCLK

tHIGH

SCLK pulse width high

tLOW

SCLK pulse width low

tEN_SDIO

Time required for the SDIO pin to switch from an input to an output

relative to the SCLK falling edge

tDIS_SDIO

Time required for the SDIO pin to switch from an output to an input

relative to the SCLK rising edge

SPORT TIMING REQUIREMENTS

tCSSCLK

Delay from the rising edge of CLK+ to the rising edge of SMI SCLK

3.2

4.5

6.2

tSSCLKSDO

Delay from the rising edge of SMI SCLK to SMI SDO

−0.4

0.4

tSSCLKSDFS

Delay from the rising edge of SMI SCLK to SMI SDFS

−0.4

0.4

TIMING DIAGRAMS

CLK+

DCOA/DCOB

CH A/CH B DATA

N+ 1

N+ 2

N+ 3

N+ 4

N+ 5

N+ 6

N+ 7

N+ 8

N – 12

N – 11

N – 9

N – 8

N – 7

N – 6

N – 5

N – 4

N – 13

CLK–

tCLK

tPD

tDCO

tCLK

CH A/CH B FAST

DETECT

N – 1

N + 2

N + 3

N + 4

N + 5

N + 6

N – 3

N – 2

N – 10

N + 1

Figure 2. CMOS Output Mode Data and Fast Detect Output Timing

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