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AD9600 Datasheet(PDF) 33 Page - Analog Devices |
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AD9600 Datasheet(HTML) 33 Page - Analog Devices |
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33 / 73 page ![]() AD9600 Rev. B | Page 32 of 72 Increment Gain (IG) and Decrement Gain (DG) The increment gain and decrement gain indicators are intended to be used together to provide information to enable external gain control. The decrement gain indicator works in conjunction with the coarse upper threshold bits, asserting when the input magnitude is greater than the 3-bit value in the coarse upper threshold register (Address 0x105). The increment gain indicator, similarly, corresponds with the fine lower threshold bits, except that it is asserted only if the input magnitude is less than the value programmed in the fine lower threshold register after the dwell time elapses. This dwell time is set by the 16-bit increase gain dwell time register (Address 0x10A and Address 0x10B) and is in units of ADC input clock cycles ranging from 1 to 65,535. The fine lower threshold register is a 13-bit register that is compared with the magnitude at the output of the ADC. This comparison is subject to the ADC clock latency but allows a finer, more accurate comparison. The fine threshold magnitude is defined in Equation 1 (see the Fine Upper Threshold (F_UT) section). The decrement gain output is influenced by the fast detect output pins, which provide a fast indication of potential overrange conditions. Assertion of the increment gain indicator is based on the comparison at the output of the ADC, requiring the input magnitude to remain below an accurate, programmable level for a predefined period before signaling external circuitry to increase the gain. The operation of the IG and DG indicators is shown in Figure 66. UPPER THRESHOLD (COARSE OR FINE) FINE LOWER THRESHOLD IG DG F_LT C_UT OR F_UT* DWELL TIME TIMER RESET BY RISE ABOVE F_LT TIMER COMPLETES BEFORE SIGNAL RISES ABOVE F_LT NOTE: OUTPUTS FOLLOW THE INSTANTANEOUS SIGNAL LEVEL AND NOT THE ENVELOPE BUT ARE GUARANTEED ACTIVE FOR A MINIMUM OF TWO ADC CLOCK CYCLES. *C_UT AND F_UT DIFFER ONLY IN ACCURACY AND LATENCY. DWELL TIME Figure 66. Threshold Settings for C_UT, F_UT, F_LT, IG, and DG |
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