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Data Sheet

AD9215

Rev. B | Page 15 of 36

when changing from 2 V p-p mode to 1 V p-p mode.

The SHA may be driven from a source that keeps the signal

peaks within the allowable range for the selected reference volt-

age. The minimum and maximum common-mode input levels

are defined as

VCMMIN = VREF/2

VCMMAX = (AVDD + VREF)/2

The minimum common-mode input level allows the AD9215 to

accommodate ground-referenced inputs.

Although optimum performance is achieved with a differential

input, a single-ended source may be driven into VIN+ or VIN−.

In this configuration, one input accepts the signal, while the

opposite input should be set to midscale by connecting it to an

appropriate reference. For example, a 2 V p-p signal may be

applied to VIN+ while a 1 V reference is applied to VIN−. The

AD9215 then accepts a signal varying between 2 V and 0 V. In

the single-ended configuration, distortion performance may

degrade significantly as compared to the differential case. How-

ever, the effect is less noticeable at lower input frequencies.

Differential Input Configurations

As previously detailed, optimum performance is achieved while

driving the AD9215 in a differential input configuration. For

baseband applications, the AD8138 differential driver provides

excellent performance and a flexible interface to the ADC. The

output common-mode voltage of the AD8138 is easily set to

AVDD/2, and the driver can be configured in a Sallen Key filter

topology to provide band limiting of the input signal.

AD8138

AD9215

VIN+

VIN–

AVDD

AGND

1V p-p

499

Ω

499

Ω

499

Ω

523

Ω

49.9

Ω

0.1

µF

VCM

Figure 32. Differential Input Configuration Using the AD8138

At input frequencies in the second Nyquist zone and above, the

performance of most amplifiers is not adequate to achieve the

true performance of the AD9215. This is especially true in IF

undersampling applications where frequencies in the 70 MHz to

200 MHz range are being sampled. For these applications, differ-

ential transformer coupling is the recommended input configura-

tion. The value of the shunt capacitor is dependant on the input

frequency and source impedance and should be reduced or re-

moved. An example of this is shown in Figure 33.

AD9215

VIN+

VIN–

AVDD

AGND

2V p-p

49.9

Ω

0.1

µF

AVDD

Ω

Figure 33. Differential Transformer-Coupled Configuration

The signal characteristics must be considered when selecting a

transformer. Most RF transformers saturate at frequencies

below a few MHz, and excessive signal power can also cause

core saturation, which leads to distortion.

Single-Ended Input Configuration

A single-ended input may provide adequate performance in

cost-sensitive applications. In this configuration, there is a deg-

radation in SFDR and distortion performance due to the large

input common-mode swing. However, if the source impedances

on each input are kept matched, there should be little effect on

SNR performance. Figure 34 details a typical single-ended input

configuration.

2V p-p

49.9

Ω

0.1

µF

0.1

µF

AD9215

VIN+

VIN–

AVDD

AGND

AVDD

Ω

Figure 34. Single-Ended Input Configuration

CLOCK INPUT AND CONSIDERATIONS

Typical high speed ADCs use both clock edges to generate a

variety of internal timing signals, and as a result may be sensi-

tive to clock duty cycle. Commonly, a 5% tolerance is required

on the clock duty cycle to maintain dynamic performance char-

acteristics. The AD9215 contains a clock duty cycle stabilizer

that retimes the nonsampling edge, providing an internal clock

signal with a nominal 50% duty cycle. This allows a wide range

of clock input duty cycles without affecting the performance of

the AD9215. As shown in Figure 25, noise and distortion per-

formance are nearly flat over a 50% range of duty cycle. For best

ac performance, enabling the duty cycle stabilizer is recom-

mended for all applications.

The duty cycle stabilizer uses a delay-locked loop (DLL) to cre-

ate the nonsampling edge. As a result, any changes to the sam-

pling frequency require approximately 100 clock cycles to allow

the DLL to acquire and lock to the new rate.

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