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PMWD18UN Datasheet(PDF) 6 Page - NXP Semiconductors |
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PMWD18UN Datasheet(HTML) 6 Page - NXP Semiconductors |
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6 / 12 page ![]() Philips Semiconductors PMWD18UN Dual N-channel µTrenchMOS™ ultra low level FET Product data Rev. 02 — 23 February 2004 6 of 12 9397 750 12706 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Tj =25 °CTj =25 °C and 150 °C; VDS ≥ ID × RDSon Fig 5. Output characteristics: drain current as a function of drain-source voltage; typical values. Fig 6. Transfer characteristics: drain current as a function of gate-source voltage; typical values. Tj =25 °C Fig 7. Drain-source on-state resistance as a function of drain current; typical values. Fig 8. Normalized drain source on-state resistance factor as a function of junction temperature. 003aaa260 0 1 2 3 4 5 0 0.2 0.4 0.6 0.8 1 VDS (V) ID (A) 1 V 1.1 V 1.2 V VGS = 1.3 V 1.8 V 4.5 V 003aaa261 0 2 4 6 8 10 0 0.5 1 1.5 2 VGS (V) ID (A) Tj = 150 °C 25 °C 003aaa262 0 40 80 120 160 01 23 45 ID (A) RDSon (m Ω) 2.5 V 1.1 V 1.2 V 1.3 V 4.5 V VGS = 1.8 V 03aa27 0 0.5 1 1.5 2 -60 0 60 120 180 Tj (°C) a a R DSon R DSon 25 °C () ------------------------------ = |
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