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PMWD18UN Datasheet(PDF) 7 Page - NXP Semiconductors |
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PMWD18UN Datasheet(HTML) 7 Page - NXP Semiconductors |
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7 / 12 page ![]() Philips Semiconductors PMWD18UN Dual N-channel µTrenchMOS™ ultra low level FET Product data Rev. 02 — 23 February 2004 7 of 12 9397 750 12706 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. ID = 1 mA; VDS =VGS Tj =25 °C; VDS =5V Fig 9. Gate-source threshold voltage as a function of junction temperature. Fig 10. Sub-threshold drain current as a function of gate-source voltage. VGS = 0 V; f = 1 MHz Tj =25 °C and 150 °C; VGS =0V Fig 11. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values. Fig 12. Source (diode forward) current as a function of source-drain (diode forward) voltage; typical values. 03aj65 0 0.2 0.4 0.6 0.8 1 -60 0 60 120 180 Tj (°C) VGS(th) (V) min typ 03aj64 10-6 10-5 10-4 10-3 0 0.2 0.4 0.6 0.8 1 VGS (V) ID (A) min typ 003aaa263 10 102 103 104 10 1 10 102 VDS (V) C (pF) Ciss Coss Crss 003aaa264 0 1 2 3 4 5 0 0.2 0.4 0.6 0.8 1 VSD (V) IS (A) 25 °C Tj = 150 °C |
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