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PMWD18UN Datasheet(PDF) 1 Page - NXP Semiconductors |
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PMWD18UN Datasheet(HTML) 1 Page - NXP Semiconductors |
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1 / 12 page ![]() PMWD18UN Dual N-channel µTrenchMOS™ ultra low level FET Rev. 02 — 23 February 2004 Product data M3D647 1. Product profile 1.1 Description Dual common drain N-channel enhancement mode field-effect transistor in a plastic package using TrenchMOS™ technology. 1.2 Features 1.3 Applications 1.4 Quick reference data 2. Pinning information s Surface mounted package s Low profile s Very low threshold s Fast switching. s Portable appliances s PCMCIA cards s Battery management s Load switching. s VDS ≤ 30 V s ID ≤ 7.8 A s Ptot ≤ 2.3 W s RDSon ≤ 21.5 mΩ. Table 1: Pinning - SOT530-1 (TSSOP8), simplified outline and symbol Pin Description Simplified outline Symbol 1,8 drain (d) SOT530-1 (TSSOP8) 2,3 source1 (s1) 4 gate1 (g1) 5 gate2 (g2) 6,7 source2 (s2) MBK885 Top view 14 85 mbl600 d d g1 s1 g2 s2 |
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