AD7150_17 datasheet(9/29 Pages) AD

9 / 29 page

AD7150

Rev. 0 | Page 8 of 28

500

–500

–250

250

11000

100

RESISTANCE CIN TO GND (MΩ)

Figure 10. Capacitance Input Offset Error vs. Resistance CIN to GND,

VDD = 3.3 V, EXC Pin Open Circuit

–10

–5

11000

100

RESISTANCE CIN TO GND (MΩ)

RESISTANCE EXC TO GND (MΩ)

Figure 11. Capacitance Input Gain Error vs. Resistance CIN to GND,

VDD = 3.3 V, CIN to EXC = 2 pF

–10

–5

010

0.50

–0.50

–0.25

0.25

010

RESISTANCE EXC TO GND (MΩ)

–8

–6

–4

–2

0250

200

150

100

SERIAL RESISTANCE (kΩ)

Figure 12. Capacitance Input Offset Error vs. Resistance EXC to GND,

VDD = 3.3 V, CIN Pin Open Circuit

Figure 13. Capacitance Input Gain Error vs. Resistance EXC to GND,

VDD = 3.3 V, CIN to EXC = 2 pF

Figure 14. Capacitance Input Gain Error vs. Serial Resistance,

VDD = 3.3 V, CIN to EXC = 2 pF

–10

–5

11000

100

PARALLEL RESISTANCE (MΩ)

Figure 15. Capacitance Input Gain Error vs. Parallel Resistance,

VDD = 3.3 V, CIN to EXC = 2 pF

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