AD7152 datasheet(20/24 Pages) AD

20 / 24 page

AD7152/AD7153

Data Sheet

Rev. A | Page 20 of 24

DIFFERENTIAL CAPACITIVE INPUT

When configured for differential mode (the CAPDIFF bit in the

Channel 1 Setup or Channel 2 Setup registers is set to 1), the

CDC measures the difference between positive and negative

capacitance input.

Each of the two input capacitances, CX and CY, between the

EXC and CIN pins must be less than 2 pF (without using the

CAPDACs) or must be less than 9 pF and balanced by the

CAPDACs. Balancing by the CAPDACs means that both

CX − CAPDAC(+) and CY − CAPDAC(−) are less than 2 pF.

If the unbalanced capacitance between the EXC and CIN pins

is higher than 2 pF, the CDC introduces a gain error, an offset

error, and nonlinearity error (see Figure 32, Figure 33, and

Figure 34).

0x0000 ... 0xFFF0

DATA

CAPDIFF = 1

±2pF

CDC

EXC

CIN(+)

CIN(–)

0pF TO 4pF

CAPDAC(+)

OFF

CAPDAC(–)

OFF

Figure 32. CDC Differential Input Mode

0x0000 ... 0xFFF0

DATA

CAPDIFF = 1

±2pF

CDC

EXC

CIN(+)

CIN(–)

4pF TO 6pF

(5 ± 1pF)

4pF TO 6pF

(5 ± 1pF)

CAPDAC(+)

5pF

CAPDAC(–)

5pF

Figure 33. Using CAPDAC in Differential Mode

0x0000 ... 0xFFF0

DATA

CAPDIFF = 1

±2pF

CDC

EXC

CIN(+)

CIN(–)

3pF TO 7pF

(5 ± 2pF)

5pF

CAPDAC(+)

5pF

CAPDAC(–)

5pF

Figure 34. Using CAPDAC in Differential Mode

PARASITIC CAPACITANCE TO GROUND

DATA

CDC

EXC

CGND1

CIN

CGND2

Figure 35. Parasitic Capacitance to Ground

The CDC architecture used in the AD7152/AD7153 measures

CX connected between the EXC pin and the CIN pin. In theory,

any capacitance, CGND, to ground should not affect the CDC

result (see Figure 35).

The practical implementation of the circuitry in the chip

implies certain limits and the result is gradually affected by

capacitance to ground. See the allowed capacitance to GND

in the Specifications table and, Figure 9 through Figure 12.

PARASITIC RESISTANCE TO GROUND

DATA

CDC

EXC

RGND1

CIN

RGND2

Figure 36. Parasitic Resistance to Ground

The CDC result can be affected by a leakage current from the

CX to ground; therefore, the CX should be isolated from the

ground. The influence of the leakage current varies with the

power supply voltage (see Figure 36).

A higher leakage current to ground results in a gain error, an

offset error, and a nonlinearity error (see Figure 13 and Figure 14).

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