COP684EG datasheet(21/48 Pages) NSC

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Multi-Input Wakeup (Continued)

The Multi-Input Wakeup feature utilizes the L Port The user

selects which particular L port bit (or combination of L Port

bits) will cause the device to exit the HALT or IDLE modes

The selection is done through the Reg WKEN The Reg

WKEN is an 8-bit readwrite register which contains a con-

trol bit for every L port bit Setting a particular WKEN bit

enables a Wakeup from the associated L port pin

The user can select whether the trigger condition on the

selected L Port pin is going to be either a positive edge (low

to high transition) or a negative edge (high to low transition)

This selection is made via the Reg WKEDG which is an 8-

bit control register with a bit assigned to each L Port pin

Setting the control bit will select the trigger condition to be a

negative edge on that particular L Port pin Resetting the bit

selects the trigger condition to be a positive edge Changing

an edge select entails several steps in order to avoid a

pseudo Wakeup condition as a result of the edge change

First the associated WKEN bit should be reset followed by

the edge select change in WKEDG Next the associated

WKPND bit should be cleared followed by the associated

WKEN bit being re-enabled

An example may serve to clarify this procedure Suppose

we wish to change the edge select from positive (low going

high) to negative (high going low) for L Port bit 5 where bit 5

has previously been enabled for an input interrupt The pro-

gram would be as follows

RBIT

WKEN

SBIT

WKEDG

RBIT

WKPND

SBIT

WKEN

If the L port bits have been used as outputs and then

changed to inputs with Multi-Input WakeupInterrupt a safe-

ty procedure should also be followed to avoid inherited

pseudo wakeup conditions After the selected L port bits

have been changed from output to input but before the as-

sociated WKEN bits are enabled the associated edge se-

lect bits in WKEDG should be set or reset for the desired

edge selects followed by the associated WKPND bits being

cleared

This same procedure should be used following reset since

the L port inputs are left floating as a result of reset

The occurrence of the selected trigger condition for Multi-In-

put Wakeup is latched into a pending register called

WKPND The respective bits of the WKPND register will be

set on the occurrence of the selected trigger edge on the

corresponding Port L pin The user has the responsibility of

clearing these pending flags Since WKPND is a pending

the device will not enter the HALT mode if any Wakeup bit is

both enabled and pending Consequently the user has the

responsibility of clearing the pending flags before attempt-

ing to enter the HALT mode

WKEN WKPND and WKEDG are all readwrite registers

and are cleared at reset

PORT L INTERRUPTS

Port L provides the user with an additional eight fully select-

able edge sensitive interrupts which are all vectored into

the same service subroutine

The interrupt from Port L shares logic with the wake up cir-

cuitry The register WKEN allows interrupts from Port L to

be individually enabled or disabled The register WKEDG

specifies the trigger condition to be either a positive or a

negative edge Finally the register WKPND latches in the

pending trigger conditions

The GIE (Global Interrupt Enable) bit enables the interrupt

function

A control flag LPEN functions as a global interrupt enable

for Port L interrupts Setting the LPEN flag will enable inter-

rupts and vice versa A separate global pending flag is not

needed since the register WKPND is adequate

Since Port L is also used for waking the device out of the

HALT or IDLE modes the user can elect to exit the HALT or

IDLE modes either with or without the interrupt enabled If

he elects to disable the interrupt then the device will restart

execution from the instruction immediately following the in-

struction that placed the microcontroller in the HALT or

IDLE modes In the other case the device will first execute

the interrupt service routine and then revert to normal oper-

ation

The Wakeup signal will not start the chip running immediate-

ly since crystal oscillators or ceramic resonators have a fi-

nite start up time The IDLE Timer (T0) generates a fixed

delay to ensure that the oscillator has indeed stabilized be-

fore allowing the device to execute instructions In this case

upon detecting a valid Wakeup signal only the oscillator

circuitry and the IDLE Timer T0 are enabled The IDLE Tim-

er is loaded with a value of 256 and is clocked from the tc

instruction cycle clock The tc clock is derived by dividing

down the oscillator clock by a factor of 10 A Schmitt trigger

following the CKI on-chip inverter ensures that the IDLE tim-

er is clocked only when the oscillator has a sufficiently large

amplitude to meet the Schmitt trigger specifications This

Schmitt trigger is not part of the oscillator closed loop The

startup timeout from the IDLE timer enables the clock sig-

nals to be routed to the rest of the chip

If the RC clock option is used the fixed delay is under soft-

ware control A control flag CLKDLY in the G7 configura-

tion bit allows the clock start up delay to be optionally insert-

ed Setting CLKDLY flag high will cause clock start up delay

to be inserted and resetting it will exclude the clock start up

delay The CLKDLY flag is cleared during reset so the clock

start up delay is not present following reset with the RC

clock options

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