COP684EG datasheet(29/48 Pages) NSC

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Interrupts (Continued)

Arbitration

Vector

Ranking

Source

Description

Address

Hi-Low Byte

(1) Highest

Software

INTR Instruction

0yFE – 0yFF

Reserved

for Future Use

0yFC – 0yFD

(2)

External

Pin G0 Edge

0yFA – 0yFB

(3)

Timer T0

Underflow

0yF8 – 0yF9

(4)

Timer T1

T1AUnderflow

0yF6 – 0yF7

(5)

Timer T1

T1B

0yF4 – 0yF5

(6)

MICROWIREPLUS

BUSY Goes Low

0yF2 – 0yF3

Reserved

for Future Use

0yF0 – 0yF1

(7)

UART

Receive

0yEE – 0yEF

(8)

UART

Transmit

0yEC – 0yED

(9)

Timer T2

T2AUnderflow

0yEA – 0yEB

(10)

Timer T2

T2B

0yE8 – 0yE9

(11)

Timer T3

T3AUnderflow

0yE6 – 0yE7

(12)

Timer T3

T3B

0yE4 – 0yE5

(13)

Port LWakeup

Port L Edge

0yE2 – 0yE3

(14) Lowest

Default

VIS Instr Execution

0yE0 – 0yE1

without Any Interrupts

y is VIS page y i 0

Inside the interrupt service routine the associated pending

bit has to be cleared by software The RETI (Return from

Interrupt) instruction at the end of the interrupt service rou-

tine will set the GIE (Global Interrupt Enable) bit allowing

the processor to be interrupted again if another interrupt is

active and pending

The VIS instruction looks at all the active interrupts at the

time it is executed and performs an indirect jump to the

beginning of the service routine of the one with the highest

rank

The addresses of the different interrupt service routines

called vectors are chosen by the user and stored in ROM in

a table starting at 01E0 (assuming that VIS is located be-

tween 00FF and 01DF) The vectors are 15-bit wide and

therefore occupy 2 ROM locations

VIS and the vector table must be located in the same 256-

byte block (0y00 to 0yFF) except if VIS is located at the last

address of a block In this case the table must be in the

next block The vector table cannot be inserted in the first

256-byte block (y i 0)

The vector of the maskable interrupt with the lowest rank is

located at 0yE0 (Hi-Order byte) and 0yE1 (Lo-Order byte)

and so forth in increasing rank number The vector of the

maskable interrupt with the highest rank is located at 0yFA

(Hi-Order byte) and 0yFB (Lo-Order byte)

The Software Trap has the highest rank and its vector is

located at 0yFE and 0yFF

If by accident a VIS gets executed and no interrupt is ac-

tive then the PC (Program Counter) will branch to a vector

located at 0yE0 – 0yE1

WARNING

A Default VIS interrupt handler routine must be present As

a minimum this handler should confirm that the GIE bit is

cleared (this indicates that the interrupt sequence has been

taken) take care of any required housekeeping restore

context and return Some sort of Warm Restart procedure

should be implemented These events can occur without

any error on the part of the system designer or programmer

Note

There is always the possibility of an interrupt occurring during an

instruction which is attempting to reset the GIE bit or any other inter-

rupt enable bit If this occurs when a single cycle instruction is being

used to reset the interrupt enable bit the interrupt enable bit will be

reset but an interrupt may still occur This is because interrupt pro-

cessing is started at the same time as the interrupt bit is being reset

To avoid this scenario the user should always use a two- three- or

four-cycle instruction to reset interrupt enable bits

Figure 15 shows the Interrupt block diagram

SOFTWARE TRAP

The Software Trap (ST) is a special kind of non-maskable

interrupt which occurs when the INTR instruction (used to

acknowledge interrupts) is fetched from ROM and placed

inside the instruction register This may happen when the

PC is pointing beyond the available ROM address space or

when the stack is over-popped

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