AD9877-EB datasheet(15/37 Pages) AD

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AD9877

Rev. B | Page 14 of 36

After passing through the half-band filter stages, the IQ data

streams are fed to a cascaded integrator-comb (CIC) filter. This

filter is configured as an interpolating filter, which allows

further upsampling rates of 3 or 4. The CIC filter, like the half-

bands, has a built-in low-pass characteristic. Again, this

provides for suppression of the spectral images produced by the

upsampling process.

The digital quadrature modulator stage following the CIC filters

is used to frequency shift (upconvert) the baseband spectrum of

the incoming data stream up to the desired carrier frequency.

The carrier frequency is controlled numerically by a direct

digital synthesizer (DDS). The DDS uses the internal system

clock (fSYSCLK) to generate the desired carrier frequency with a

high degree of precision. The carrier is applied to the I and Q

multipliers in quadrature fashion (90° phase offset) and

summed to yield a data stream that is the modulated carrier.

It should be noted at this point that the incoming data has been

converted from an input sample rate of fMCLK to an output

sample rate of fSYSCLK (see Figure 15). The modulated carrier

becomes the 12-bit samples sent to the DAC.

Single-Tone Output Transmit Operation

The AD9877 can be configured for frequency synthesis

applications by writing the single-tone bit true. In single-tone

mode, the AD9877 disengages the modulator and preceding

data path logic to output a spectrally pure single-frequency sine

wave. The AD9877 provides for a 26-bit frequency tuning word,

which results in a tuning resolution of 3.2 Hz at a fSYSCLK rate of

216 MHz. A good rule when using the AD9877 as a frequency

synthesizer is to limit the fundamental output frequency to 30%

of fSYSCLK. This avoids generating aliases too close to the desired

fundamental output frequency, thus minimizing the cost of

filtering the aliases.

Frequency hopping via the profile inputs and associated tuning

word is also supported in single-tone mode, which allows

frequency shift keying (FSK) modulation.

OSCIN Clock Multiplier

As mentioned earlier, the output data is sampled at the rate of

fSYSCLK. The AD9877 has a built-in programmable clock

multiplier and an oscillator circuit. This allows the use of a

relatively low frequency, and therefore less expensive, crystal or

oscillator to generate the OSCIN signal. The low frequency

OSCIN signal can then be multiplied in frequency by an integer

factor of between 1 and 31, inclusive, to become the fSYSCLK clock.

For DDS applications, the carrier is typically limited to about

30% of fSYSCLK. For a 65 MHz carrier, the system clock required is

above 216 MHz.

The OSCIN multiplier function maintains clock integrity, as

evidenced by the excellent phase noise characteristics and low

clock-related spur in the output spectrum of the AD9877.

External loop filter components consisting of a series resistor

(1.3 kΩ) and capacitor (0.01 μF) provide the compensation zero

for the OSCIN multiplier PLL loop. The overall loop

performance has been optimized for these component values.

Receive Section

The AD9877 includes three high speed, high performance

ADCs. Two matched 8-bit ADCs are optimized for analog IQ

demodulated signals and can be sampled at rates up to

16.5 MSPS. A direct IF 12-bit ADC can sample signals at rates

up to 33 MSPS.

The ADC sampling frequency can be derived directly from the

OSCIN signal or from the on-chip OSCIN multiplier. For

highest dynamic performance, it is recommended to choose an

OSCIN frequency that can be directly used as the ADC

sampling clock. Digital 8-bit ADC outputs are multiplexed to

one 4-bit bus, clocked by the master clock (MCLK). The 12-bit

ADC uses a nonmultiplexed 12-bit interface with an output

data rate of half the fMCLK frequency.

CLOCK AND OSCILLATOR CIRCUITRY

The internal oscillator of the AD9877 generates all sampling

clocks from a simple, low cost, parallel resonance, fundamental

frequency quartz crystal. Figure 16 shows how the quartz

crystal is connected between OSCIN (Pin 61) and XTAL

(Pin 60) with parallel resonant load capacitors as specified by

the crystal manufacturer. The internal oscillator circuitry can

also be overdriven by a clock applied to OSCIN with XTAL left

unconnected.

fOSCIN = fMCLK × N/M

An internal phase-locked loop (PLL) generates the DAC

sampling frequency, fSYSCLK, by multiplying OSCIN frequency M

times. The MCLK signal (Pin 23), fMCLK, is derived by dividing

this PLL output frequency by N (Register Address 0x01).

fSYSCLK = fOSCIN × M

fMCLK = fOSCIN × M/N

An external PLL loop filter (Pin 57) consisting of a series

resistor and ceramic capacitor (Figure 16, R1 = 1.3 kΩ, C12 =

0.01 μF) is required for stability of the PLL. Also, a shield

surrounding these components is recommended to minimize

external noise coupling into the PLL’s voltage-controlled

oscillator input (guard trace connected to AVDDPLL).

Figure 15 shows that ADCs are either sampled directly by a low

jitter clock at OSCIN or by a clock that is derived from the PLL

output. Operating modes can be selected in Register 0x08.

Sampling the ADCs directly with the OSCIN clock requires

MCLK to be programmed at twice the OSCIN frequency.

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