AD9877-EB datasheet(30/37 Pages) AD

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AD9877

Rev. B | Page 29 of 36

PROGRAMMING THE AD8321/AD8325 OR AD8322/AD8327 CABLE DRIVER AMPLIFIER

GAIN CONTROL

Programming the gain of the AD832x family cable driver

amplifier can be accomplished via the AD9877 cable amplifier

control interface. Four 8-bit registers within the AD9877 (one

per profile) store the gain value to be written to the serial 3-wire

port. Typically either AD8321/AD8325 or AD8322/AD8327

variable gain cable amplifiers are connected to the chip’s 3-wire

cable amplifier interface. The Tx gain control select bit in

0x13, 0x17, 0x1B, and 0x1F. See the Cable Driver Gain Control

section register description.

Data transfers to the gain programmable cable driver amplifier

are initiated by the following four conditions.

Power-Up and Hardware Reset—Upon initial power-up

and every hardware reset, the AD9877 clears the contents

of the gain control registers to 0, which defines the lowest

gain setting of the AD832x. Thus, the AD9877 writes all 0s

out of the 3-wire cable amplifier control interface.

Software Reset—Writing a 1 to Bit 5 of Address 0x00

initiates a software reset. Upon a software reset, the

AD9877 clears the contents of the gain control registers to

0 for the lowest gain and sets the profile select to 0. The

AD9877 writes all 0s out of the 3-wire cable amplifier

control interface if the gain was previously on a different

setting (other than 0).

Change in Profile Selection—The AD9877 samples the

PROFILE(1) and PROFILE(2) input pins together with the

two profile select bits and writes to the AD832x gain

control registers if a change in profile and gain is

determined. The data written to the cable driver amplifier

comes from the AD9877 gain control register associated

with the current profile.

Write to AD9877 Cable Driver Amplifier Control

Registers—The AD9877 will write gain control data

associated with the current profile to the AD832x

whenever the selected AD9877 cable driver amplifier gain

setting is changed.

Once a new stable gain value has been detected (48 MCLK to

64 MCLK cycles after initiation), a data write starts with CA_CS

going low. The AD9877 always finishes a write sequence to the

cable driver amplifier once it is started. The logic controlling

data transfers to the cable driver amplifier uses up to 200 MCLK

cycles and is designed to prevent erroneous write cycles from

occurring.

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