AD9877-EB datasheet(29/37 Pages) AD

29 / 37 page

AD9877

Rev. B | Page 28 of 36

The AD9877 provides true and complement current outputs.

The full-scale output current is set by the RSET resistor at Pin 49

and the DAC gain register. Assuming maximum DAC gain, the

value of RSET for a particular full-scale IOUT is determined using

the following equation:

RSET = 32 VDACRSET/IOUT = 39.4/IOUT

For example, if a full-scale output current of 20 mA is desired,

then RSET = (39.4/0.02) Ω or approximately 2 kΩ.

The following equation calculates the full-scale output current,

including the programmable DAC gain control.

IOUT = [39.4/RSET] × 10(−7.5 + 0.5 NGAIN)/20

where NGAIN is the value of DAC fine gain control [3:0].

The full-scale output current range of the AD9877 is 4 to

20 mA. Full-scale output currents outside of this range degrade

SFDR performance. SFDR is also slightly affected by output

matching; the two outputs should be terminated equally for best

SFDR performance. The output load should be located as close

as possible to the AD9877 package to minimize stray

capacitance and inductance. The load can be a simple resistor to

ground, an op amp current-to-voltage converter, or a

transformer-coupled circuit. It is best not to attempt to directly

drive highly reactive loads (such as an LC filter). Driving an LC

filter without a transformer requires that the filter be doubly

terminated for best performance.

The filter input and output should both be resistively

terminated with the appropriate values. The parallel

combination of the two terminations will determine the load

that the AD9877 will see for signals within the filter pass band.

For example, a 50 Ω terminated input/output low-pass filter will

look like a 25 Ω load to the AD9877. The output compliance

voltage of the AD9877 is −0.5 V to +1.5 V. To avoid signal

distortion, any signal developed at the DAC output should not

exceed 1.5 V. Furthermore, the signal may extend below ground

as much as 0.5 V without damage or signal distortion.

The AD9877 true and complement outputs can be differentially

combined for common-mode rejection using a broadband 1:1

transformer. Using a grounded center tap results in signals at

the AD9877 DAC output pins that are symmetrical about

ground. As previously mentioned, by differentially combining

the two signals, the user can provide some degree of common-

mode signal rejection. A differential combiner might consist of

a transformer or an operational amplifier. The object is to

combine or amplify only the difference between two signals and

to reject any common, usually undesirable characteristic, such

as 60 Hz hum or clock feedthrough that is equally present on

both individual signals.

Connecting the AD9877 true and complement outputs to the

differential inputs of the gain programmable cable drivers

AD8321/AD8323 or AD8322/AD8327 provides an optimized

solution for the standard compliant cable modem upstream

channel. The cable driver’s gain can be programmed through a

direct 3-wire interface using the profile registers of the AD9877.

LOW-PASS

FILTER

AD832x

AD9877

VARIABLE GAIN

CABLE DRIVER

AMPLIFIER

CA_EN

CA_DATA

CA_CLK

DAC

Figure 37. Cable Amplifier Connection

CA_EN

CA_CLK

CA_DATA

MSB

tMCLK

LSB

Figure 38. Cable Amplifier Interface Timing

AD9877-EB Datasheet(PDF) 29 Page - Analog Devices

AD9877-EB Datasheet(HTML) 29 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37

Datasheet Download

Link URL