© 2006 Fairchild Semiconductor Corporation

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FMS6406 Rev. 4.0.4

Functional Description

Introduction

This product is a two channel monolithic continuous time

video filter designed for reconstructing the luminance and

chrominance signals from an S-Video D/A source.

Composite video output is generated by summing the Y

and C outputs. The chip is designed to have AC coupled

inputs and will work equally well with either AC or DC

coupled outputs.

The reconstruction filters provide a 5th-order Butterworth

response with group delay equalization. This provides a

maximally flat response in terms of delay and amplitude.

75Ω load.

All channels are clamped during the sync interval to set the

appropriate minimum output DC level. With this operation

the effective input time constant is greatly reduced, which

allows for the use of small low cost coupling capacitors.

The net effect is that the input will settle to 10mV in 5ms

for any DC shifts present in the input video signal.

In most applications the input coupling capacitors are

0.1μF. The Y and C inputs typically sink 1μA of current

during active video, which normally tilts a horizontal line

by 2mV at the Y output. During sync, the clamp restores

this leakage current by sourcing an average of 20μA over

the clamp interval. Any change in the coupling capacitor

values will affect the amount of tilt per line. Any reduction

in tilt will come with an increase in settling time.

Luminance (Y) I/O

The typical luma input is driven by either a low impedance

driven by the output of a current DAC. In either case, the

input must be capacitively coupled to allow the sync-

detect and DC restore circuitry to operate properly.

into either a single or dual video load. A single video load

consists of a series 75Ω impedance matching resistor

connected to a terminated 75Ω line, this presents a total

of 150Ω of loading to the part. A dual load would be two of

these in parallel which would present a total of 75Ω to the

input levels. Even when two loads are present the driver

Chrominance (C) I/O

The chrominance input can be driven in the same manner

Since the chrominance signal doesn’t contain any DC

content, the output signal can be AC coupled using as

small as a 0.1μF capacitor if DC-coupling is not desired.

Composite Video (CV) Output

The composite video output driver is same as the other

outputs. When driving a dual load either output will still

function if the other output connection is inadvertently

shorted providing these loads are AC-coupled.

Equalizer/Notch (EQ_NOTCH) Output

which will meet its primary intention of driving a modulator

load.

Layout Considerations

General layout and supply bypassing play major roles in

high-frequency performance and thermal characteristics.

The FMS6406DEMO is a 4-layer board with a full power

and ground plane. Following this layout configuration will

provide the optimum performance and thermal characte-

ristics. For optimum results, follow the steps below as a

basis for high frequency layout:

Include 1μF and 0.1μF ceramic bypass capacitors

Place the 1μF capacitor within 0.75 inches of the

power pin

Place the 0.1μF capacitor within 0.1 inches of the

power pin

For multi-layer boards, use a large ground plane to

help dissipate heat

For 2-layer boards, use a ground plane that extends

beyond the device by at least 0.5”

Minimize all trace lengths to reduce series inductances

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