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MT9V024 Datasheet(PDF) 33 Page - ON Semiconductor |
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MT9V024 Datasheet(HTML) 33 Page - ON Semiconductor |
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33 / 40 page  MT9V024/D www.onsemi.com 33 Propagation Delays for FRAME_VALID and LINE_VALID Signals The LV and FV signals change on the same rising master clock edge as the data output. The LV goes HIGH on the same rising master clock edge as the output of the first valid pixel’s data and returns LOW on the same master clock rising edge as the end of the output of the last valid pixel’s data. As shown in the “Output Data Timing”, FV goes HIGH 143 pixel clocks before the first LV goes HIGH. It returns LOW 23 pixel clocks after the last LV goes LOW. Figure 39. Propagation Delays for FRAME_VALID and LINE_VALID Signals FRAME_VALID LINE_VALID FRAME_VALID LINE_VALID t PIXCLK PIXCLK P t FLR FLF PP P P Two-Wire Serial Bus Timing Detailed timing waveforms and parameters for the two−wire serial interface bus are shown in Figure 40 and Table 17. Figure 40. Two−Wire Bus Timing Parameters SDATA SCLK tf tLOW THD;STA S tr tHD;DAT tHIGH TSU;DAT tf TSU;STA Sr |
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