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Preliminary Technical Data

AD5933

Rev. PrA | Page 7 of 20

GENERAL DESCRIPTION

The AD5933 is a high precision impedance converter system

solution which combines an on board frequency generator with

a 12 Bit 1MSPS ADC. The frequency generator allows an

external complex impedance to be excited with a known

frequency. The response signal from the impedance is sampled

by the on board ADC and FFT processed by an on-board DSP

engine. The FFT algorithm returns two Real (R) and Imaginary

(I) data words. The impedance magnitude and phase is easily

calculated using the following equations:

Magnitude =

R + I

Phase = Tan (I/R)

-1

To determine the actual real impedance value Z(W) , generally a

frequency sweep is performed. The impedance can be

calculated at each point and a frequency vs magnitude plot can

be created.

Gain

Frequency

Figure 2.

The system allows the user to program a 2V PK-PK sinusoidal

signal as excitation to an external load. Output ranges of 1V,

500mV, 200mV can also be programmed. The signal is provided

on chip using DDS techniques. Frequency resolution of 27 bits

(less than 0.1HZ) can be achieved. The clock for the DDS can

be generated from an external reference clock, an internal RC

oscillator or an internal PLL. The PLL has a gain stage of 520

and typically needs a reference clock of 32KHz on the MCLK

pin.

OUTPUT STAGE

The output stage of the AD5933, shown in diagram below,

provides a constant output frequency or frequency sweep

function which has a programmable output voltage of

2/1/0.5/0.2V. The frequency sweep sequence is pre-progammed

through the I2C interface. An I2C command is used to start the

excitation sequence.

Rgain

Rload

Vdd/8

TF1

Figure 3.

CIRCUIT DESCRIPTION

The AD5933 has a fully integrated Direct Digital Synthesis

(DDS) core to generate required frequencies. The block requires

a reference clock to provide digitally created sine waves up to

50KHz. This is provided through an external reference clock,

MCLK. This clock is internally divided down by 4 to provide

the reference clock or fMCLK to the DDS.

The internal circuitry of the DDS consists of the following main

sections: a Numerical Controlled Oscillator (NCO), a

Frequency Modulator, SIN ROM and a Digital-to-Analog

Converter.

NUMERICAL CONTROLLED OSCILLATOR + PHASE

MODULATOR

The main component of the NCO is a 27-bit phase accumulator

which assembles the phase component of the output signal.

Figure 4

Continuous time signals have a phase range of 0 to 2pi. Outside

this range of numbers, the sinusoid functions repeat themselves

in a periodic manner. The digital implementation is no

different. The accumulator simply scales the range of phase

numbers into a multi-bit digital word. The phase accumulator

in the DDS is implemented with 28 bits. Therefore, 2pi = 227.

Likewise, the DPhase term is scaled into this range of numbers

0 < DPhase < 227 – 1. Making these substitutions into the

equation above

f = DPhase x fMCLK/227

where 0 < DPhase < 227 - 1.

(Note. fmclk = MCLK/4)

The input to the phase accumulator (i.e., the phase step) is

selected from the frequency register. NCOs inherently generate

continuous phase signals, thus avoiding any output

discontinuity when switching between frequencies.

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