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AD7760 Datasheet(PDF) 19 Page - Analog Devices |
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AD7760 Datasheet(HTML) 19 Page - Analog Devices |
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19 / 37 page ![]() AD7760 Rev. A | Page 18 of 36 THEORY OF OPERATION The AD7760 employs a Σ-Δ conversion technique to convert the analog input into an equivalent digital word. The modulator samples the input waveform and outputs an equivalent digital word to the digital filter at a rate equal to ICLK. By employing oversampling, the quantization noise is spread across a wide bandwidth from 0 to fICLK. This means that the noise energy contained in the signal band of interest is reduced (see Figure 40a). To further reduce the quantization noise in the signal band of interest, a high order modulator is employed to shape the noise spectrum so that most of the noise energy is shifted out of the signal band (see Figure 40b). The digital filtering that follows the modulator removes the large out-of-band quantization noise (see Figure 40c) while also reducing the data rate from fICLK at the input of the filter to fICLK/8 or less at the output of the filter, depending on the decimation rate used. Digital filtering has certain advantages over analog filtering: It does not introduce significant noise or distortion and can be made perfectly linear in terms of phase. The AD7760 employs three FIR filters in series. By using different combinations of decimation ratios, filter selection, and bypassing, data can be obtained from the AD7760 at a large range of data rates. Multibit data from the modulator can be obtained at the ICLK rate (see Modulator Data Output Mode section). The first filter receives the data from the modulator at a maximum frequency of 20 MHz and decimates it by 4 to output the data at 5 MHz. The partially filtered data can be output at this stage. The second filter allows the decimation rate to be chosen from 2× to 32× or to be completely bypassed. The third filter has a fixed decimation rate of 2×, is user programmable, and has a default configuration. It is described in detail in the Programmable FIR Filter section. This filter can also be bypassed. Table 6 shows some characteristics of the default filter. The group delay of the filter is defined to be the delay to the center of the impulse response and is equal to the computation plus the filter delays. The delay until valid data is available (the DVALID status bit is set) is equal to twice the filter delay plus the computation delay. QUANTIZATION NOISE fICLK\2 BAND OF INTEREST a. fICLK\2 NOISE SHAPING BAND OF INTEREST b. fICLK\2 BAND OF INTEREST DIGITAL FILTER CUTOFF FREQUENCY c. Figure 40. Σ-∆ ADC Table 6. Configuration with Default Filter ICLK Frequency Filter 1 Filter 2 Filter 3 Data State Computation Delay Filter Delay Pass-Band Bandwidth Output Data Rate (ODR) 20 MHz Bypassed Bypassed Bypassed Unfiltered 0 0 10 MHz 20 MHz 20 MHz 4× Bypassed Bypassed Partially filtered 0.325 µs 1.2 µs 1.35 MHz 5 MHz 20 MHz 4× Bypassed 2× Fully filtered 1.075 µs 10.8 µs 1 MHz 2.5 MHz 20 MHz 4× 2× Bypassed Partially filtered 1.35 µs 3.6 µs 562.5 kHz 2.5 MHz 20 MHz 4× 2× 2× Fully filtered 1.625 µs 22.8 µs 500 kHz 1.25 MHz 20 MHz 4× 4× Bypassed Partially filtered 1.725 µs 6 µs 281.25 kHz 1.25 MHz 20 MHz 4× 4× 2× Fully filtered 1.775 µs 44.4 µs 250 kHz 625 kHz 20 MHz 4× 8x Bypassed Partially filtered 2.6 µs 10.8 µs 140.625 kHz 625 kHz 20 MHz 4× 8× 2× Fully filtered 2.25 µs 87.6 µs 125 kHz 312.5 kHz 20 MHz 4× 16× Bypassed Partially filtered 4.175 µs 20.4 µs 70.3125 kHz 312.5 kHz 20 MHz 4× 16× 2× Fully filtered 3.1 µs 174 µs 62.5 kHz 156.25 kHz 20 MHz 4× 32× Bypassed Partially filtered 7.325 µs 39.6 µs 35.156 kHz 156.25 kHz 20 MHz 4× 32× 2× Fully filtered 4.65 µs 346.8 µs 31.25 kHz 78.125 kHz 12.288 MHz 4× 8× 2× Fully filtered 3.66 µs 142.6 µs 76.8 kHz 192 kHz 12.288 MHz 4× 16× 2× Fully filtered 5.05 µs 283.2 µs 38.4 kHz 96 kHz 12.288 MHz 4× 32× Bypassed Partially filtered 11.92 µs 64.45 µs 21.6 kHz 96 kHz 12.288 MHz 4× 32× 2× Fully filtered 7.57 µs 564.5 µs 19.2 kHz 48 kHz |
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