EVAL-AD7760EB datasheet(28/37 Pages) AD

28 / 37 page

AD7760

Rev. A | Page 27 of 36

To obtain maximum performance from the AD7760, it is

advisable to drive the ADC with differential signals. Figure 53

shows how a bipolar, single-ended signal biased around ground

can drive the AD7760 with the use of an external op amp, such

as the AD8021.

RIN

RFB

CFB

RIN

RFB

CFB

VIN–

VIN

VIN+

AD8021

Figure 53. Single-Ended-to-Differential Conversion

The AD7760 employs a double-sampling front end, as shown in

Figure 54. For simplicity, only the equivalent input circuit for VIN+

is shown. The equivalent input circuitry for VIN− is the same.

CS2

CPB2

SS4

SH4

CPA

SS2

SH2

CS1

CPB1

SS3

SH3

SS1

SH1

ANALOG

MODULATOR

VIN+

Figure 54. Equivalent Input Circuit

Sampling Switches SS1 and SS3 are driven by ICLK, whereas

Sampling Switches SS2 and SS4 are driven by ICLK. When ICLK is

high, the analog input voltage is connected to CS1. On the falling

edge of ICLK, the SS1 and SS3 switches open and the analog input

is sampled on CS1. Similarly, when ICLK is low, the analog input

voltage is connected to CS2. On the rising edge of ICLK, the SS2

and SS4 switches open and the analog input is sampled

on CS2.

Capacitors CPA, CPB1, and CPB2 represent parasitic capacitances

that include the junction capacitances associated with the MOS

switches.

Table 9. Equivalent Component Values

Mode

CS1 (pF)

CS2 (pF)

CPA (pF)

CPB1/2 (pF)

Normal

Low Power

USING THE AD7760

The following is the recommended sequence for powering up

and using the AD7760:

Apply power.

Start the clock oscillator, applying MCLK.

Take RESET low for a minimum of one MCLK cycle.

Wait a minimum of two MCLK cycles after RESET has

been released.

Write to Control Register 2 to power up the ADC and the

differential amplifier as required. The correct clock divider

(CDIV) ratio should be programmed at this time.

Write to Control Register 1 to set the output data rate.

Wait a minimum of five MCLK cycles after CS has been

released.

Take SYNC low for a minimum of four MCLK cycles, if

required, to synchronize multiple parts.

Data can then be read from the part using the default filter,

offset, gain, and overrange threshold values. The conversion

data read is not valid, however, until the group delay of the filter

has elapsed. Once this has occurred, the DVALID bit read with

the data LSW is set, indicating that the data is indeed valid.

The user can then download a different filter if required (see the

Downloading a User-Defined Filter section). Values for gain,

offset, and overrange threshold registers can be written or read

at this stage.

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