EVAL-AD7760EB datasheet(22/37 Pages) AD

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AD7760

Rev. A | Page 21 of 36

INVALID DATA

MOD DATA M

MOD DATA M + 1

MOD D...

t10

t20

DRDY

D[0:15]

MCLK

CS, RD/WR

t11

t19

t14

Figure 45. AD7760 Modulator Output Mode (CDIV = 0, n is odd)

In the case where n is an odd number of MCLK cycles, the

modulator data output on Pins D [15:0] is output on the rising

edge of DRDY. In this case, the modulator data should be read

on the falling edge of MCLK when DRDY is logic low. Figure 45

shows timing details to be used when reading the modulator

output data where CDIV = 0 and there is an odd number of

MCLK cycles between the rising edge of RESET and the rising

edge of SYNC. The edge of MCLK that should be used under

these conditions is illustrated in Figure 45 by arrows on the

MCLK falling edges in question.

USING THE AD7760

IN MODULATOR OUTPUT MODE

The following is the recommended sequence for powering up

and using the AD7760:

Apply power.

Start the clock oscillator, applying MCLK.

Take RESET low for a minimum of one MCLK cycle.

Wait a minimum of two MCLK cycles after the rising edge

of RESET.

Write to Control Register 2 to power up the ADC and the

differential amplifier as required. The correct clock divider

(CDIV) ratio should be programmed at this time.

Write to Control Register 1 to set the bypass filter bits, BYP F1

and BYP F3, and the decimation rate bits, DEC [2:0], to 0.

Wait a minimum of six MCLK cycles after the rising edge

of CS has been released.

Take SYNC low for a minimum of four MCLK cycles, if

required, to synchronize multiple parts.

Using this sequence results in an even number of MCLK cycles

between the rising edge of RESET and the rising edge of SYNC.

Therefore, when using this sequence with CDIV = 0, the interface

timing shown in Figure 43 should be implemented.

Note that whether the number of MCLK cycles between the

rising edge of RESET and SYNC is odd or even is irrelevant

when the AD7760 is operated with CDIV = 1.

When using the AD7760 in modulator output mode, the offset,

gain, and overrange registers are not operational. The only

registers that can be used are Control Register 1 and Control

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