EVAL-AD7760EB datasheet(7/37 Pages) AD

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AD7760

Rev. A | Page 6 of 36

TIMING SPECIFICATIONS

AVDD1 = DVDD = VDRIVE = 2.5 V, AVDD2 = AVDD3 = AVDD4 = 5 V, TA = 25°C, normal mode, unless otherwise noted.

Table 3.

Parameter

Limit at TMIN, TMAX

Unit

Description

fMCLK

MHz min

Applied master clock frequency

MHz max

fICLK

500

kHz min

Internal modulator clock derived from MCLK

MHz max

t11, 2

0.5 × tICLK

typ

DRDY pulse width

ns min

DRDY falling edge to CS falling edge

ns min

RD/WR setup time to CS falling edge

(0.5 × tICLK) + 16 ns

max

Data access time

tICLK

min

CS low read pulse width

tICLK

min

CS high pulse width between reads

ns min

RD/WR hold time to CS rising edge

ns max

Bus relinquish time

t92

0.5 × tICLK

typ

DRDY high period

t102

0.5 × tICLK

typ

DRDY low period

t11

(0.5 × tICLK) + 16 ns

max

Data access time

t123, 4

ns min

Data valid prior to DRDY rising edge

t133, 4

ns min

Data valid after DRDY rising edge

t14

ns max

Bus relinquish time

t15

4 × tICLK

min

CS low write pulse width

t16

4 × tICLK

min

CS high period between address and data

t17

ns min

Data setup time

t18

ns min

Data hold time

t194, 5

ns min

Data valid prior to MCLK falling edge while DRDY is logic low

t204, 5

ns min

Data valid after MCLK falling edge while DRDY is logic low

1 tICLK = 1/fICLK.

2 When ICLK = MCLK, DRDY pulse width depends on the mark-space ratio of applied MCLK.

3 Valid when using the modulator output mode with CDIV = 1.

4 See the Modulator Data Output Mode section for timing diagrams.

5 Valid when using the modulator output mode with CDIV = 0.

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