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HT86384 Datasheet(PDF) 25 Page - Holtek Semiconductor Inc |
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HT86384 Datasheet(HTML) 25 Page - Holtek Semiconductor Inc |
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25 / 39 page  HT86XXX Rev. 1.70 25 May 6, 2004 Reset Timing Chart Reset Circuit Reset Configuration The function unit chip reset status are shown below. PC 000H Interrupt Disable Prescaler Clear WDT Clear. After master reset, WDT begins counting Timer/event counter Off Input/output ports Input mode SP Points to the top of the stack Timer/Event Counter 0/1 There are four timer counters are implemented in the HT86XXX. The Timer/Event Counter 0 and 1 contain 16-bit programmable count-up counters whose clock may come from an external source or the system clock divided by 4 (T1). Using the internal instruction clock (T1), there is only one reference time base. The external clock input allows the user to count external events, measure time intervals or pulse width, or to generate an accurate time base. There are three registers related to Timer/Event Coun- ter 0; TMR0H (0CH), TMR0L (0DH), TMR0C (0EH). Writing to TMR0L only writes the data into a low byte buffer. Writing to TMR0H will write the data and the con- tents of the low byte buffer into the Timer/Event Counter 0 preload register (16-bit) simultaneously. The Timer/Event Counter 0 preload register is changed only by a write to TMR0H operation. Writing to TMR0L will keep the Timer/Event Counter 0 preload register un- changed. Reading TMR0H will also latch the TMR0L into the low byte buffer to avoid false timing problems. Reading the TMR0L only returns the value from the low byte buffer which may be a previously loaded value. In other words, the low byte of Timer/Event Counter 0 cannot be read di- rectly. It must read the TMR0H first to ensure that the low byte contents of Timer/Event Counter 0 are latched into the buffer. There are three registers related to the Timer/Event Counter 1; TMR1H (0FH), TMR1L (10H), TMR1C (11H). The Timer/Event Counter 1 operates in the same man- ner as Timer/Event Counter 0. Label Bits Function ¾ 0~2 Unused bit, read as ²0² TE 3 To define the TMR0/TMR1 active edge of timer/event counter (0=active on low to high; 1=active on high to low) TON 4 To enable/disable timer counting (0=disabled; 1=enabled) ¾ 5 Unused bit, read as ²0² TM0, TM1 6 7 To define the operating mode (TMR1, TMR0) 01=Event count mode (external clock) 10=Timer mode (internal clock) 11=Pulse width measurement mode 00=Unused TMR0C/TMR1C Register Label Bits Function ¾ 0~2 Unused bit, read as ²0² TE 3 To define the TMR0/TMR1 active edge of timer/event counter (0=active on low to high; 1=active on high to low) TON 4 To enable/disable timer counting (0=disabled; 1=enabled) ¾ 5 Unused bit, read as ²0² TM0, TM1 6 7 To define the operating mode (TMR1, TMR0) 01=Unused 10=Timer mode (internal clock) 11=Unused 00=Unused TMR2C Register t S S T R E S V D D S S T T i m e - o u t C h i p R e s e t R E S V D D W D T H A L T W D T T i m e - o u t R e s e t R E S C o l d R e s e t W a r m R e s e t P o w e r - o n D e t e c t i n g S S T 1 0 - s t a g e R i p p l e C o u n t e r O S C I |
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