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HT86384 Datasheet(PDF) 29 Page - Holtek Semiconductor Inc |
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HT86384 Datasheet(HTML) 29 Page - Holtek Semiconductor Inc |
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29 / 39 page  HT86XXX Rev. 1.70 29 May 6, 2004 Input/Output Ports There are 23 bidirectional input/output lines in the microcontroller, labeled from PA to PC, which are mapped to the data memory of [12H], [14H], and [16H] respectively. All of these I/O ports can be used for input and output operations. For input operation, these ports are non-latching, that is, the inputs must be ready at the T2 rising edge of instruction ²MOV A, [m]² (m=12H,14H or 16H). For output operation, all the data is latched and remains unchanged until the output latch is rewritten. Each I/O line has its own control register (PAC, PBC, PCC) to control the input/output configuration. With this control register, CMOS output or Schmitt trigger input with or without pull-high resistor structures can be re- configured dynamically (i.e. on-the-fly) under software control. To function as an input, the corresponding latch of the control register must write ²1². The input source also depends on the control register. If the control regis- ter bit is ²1², the input will read the pad state. If the con- trol register bit is ²0², the contents of the latches will move to the internal bus. The latter is possible in the ²read-modify-write² instruction. For output function, CMOS is the only configuration. These control registers are mapped to locations 13H, 15H, and 17H. Bit 7 which is mapped to location [17H] is always written as ²1². After a chip reset, these input/output lines remain at high levels or floating state (dependent on pull-high options). Each bit of these input/output latches can be set or cleared by ²SET [m].i² and ²CLR [m].i² (m=12H, 14H, 16H) instructions. Some instructions first input data and then follow the output operations. For example, ²SET [m].i², ²CLR [m].i ², ²CPL [m]², ²CPLA [m]² read the entire port states into the CPU, execute the defined operations (bit-operation), and then write the results back to the latches or the accumulator. Each line of port A has the capability of waking-up the device. The wake-up capability of port A is determined by mask option. There is a pull-high option available for all I/O lines. Once the pull-high option is selected, all I/O lines have pull-high resistors. Otherwise, the pull-high resistors are absent. It should be noted that a non-pull-high I/O line operating in input mode will cause a floating state. By some different mask options, there are 3 shared pins (PC.4, PC.5, and PC.6) in PC. They can be normal I/O pins or for special functions. The PC.4 is the external clock source of timer/event counter TMR0 if TMR0 is set to external clock mode, and the PC.5 is the external clock source of timer/event counter TMR1 if TMR1 is set to external clock mode. PC6 is pin-shared with XIN. The XIN and XOUT can be connected to a 32kHz crystal as the clock source of the timer counter TMR3 if the mask option is set to enable 32kHz (RTC) crystal. Q D C K S Q Q D C K S Q M U X D a t a B u s W r i t e C o n t r o l R e g i s t e r C h i p R e s e t R e a d C o n t r o l R e g i s t e r W r i t e I / O R e a d I / O S y s t e m W a k e - U p ( P A o n l y ) W e a k P u l l - u p P A 0 ~ P A 7 P B 0 ~ P B 7 P C 0 ~ P C 6 M a s k O p t i o n M a s k O p t i o n V D D V D D Input/Output Ports |
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