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Data Sheet

AD7927

Rev. D | Page 5 of 28

TIMING SPECIFICATIONS1

AVDD = 2.7 V to 5.25 V, VDRIVE ≤ AVDD, REFIN = 2.5 V; TA = TMIN to TMAX, unless otherwise noted.

Table 2.

Parameter

Limit at TMIN, TMAX AD7927

Description

AVDD = 3 V

AVDD = 5 V

Unit

fSCLK2

kHz min

MHz max

tCONVERT

16 × tSCLK

tQUIET

ns min

Minimum quiet time required between CS rising edge and start of

next conversion

ns min

CS to SCLK setup time

t33

ns max

Delay from CS until DOUT three-state disabled

t43

ns max

Data access time after SCLK falling edge

0.4 × tSCLK

ns min

SCLK low pulsewidth

0.4 × tSCLK

ns min

SCLK high pulsewidth

ns min

SCLK to DOUT valid hold time

t84

15/45

15/35

ns min/max

SCLK falling edge to DOUT high impedance

ns min

DIN setup time prior to SCLK falling edge

t10

ns min

DIN hold time after SCLK falling edge

t11

ns min

Sixteenth SCLK falling edge to CS high

t12

μs max

Power-up time from full power-down/auto shutdown mode

1 Sample tested at 25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of AVDD) and timed from a voltage level of 1.6 V,

(see Figure 2). The 3 V operating range spans from 2.7 V to 3.6 V. The 5 V operating range spans from 4.75 V to 5.25 V.

2 Mark/space ratio for the SCLK input is 40/60 to 60/40.

3 Measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.4 V or 0.7 × VDRIVE.

4 t8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated

back to remove the effects of charging or discharging the 50 pF capacitor. This means the time, quoted in the t8 timing characteristics, is the true bus relinquish time

of the part and is independent of the bus loading.

200µA

IOL

200µA

IOH

1.6V

TO OUTPUT

50pF

Figure 2. Load Circuit for Digital Output Timing Specifications

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