AD7927 datasheet(26/29 Pages) AD

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Data Sheet

AD7927

Rev. D | Page 25 of 28

For example, if the ADSP-2189 had a 20 MHz crystal such that

it had a master clock frequency of 40 MHz, then the master

cycle time would be 25 ns. If the SCLKDIV register is loaded

with the value of 3, then an SCLK of 5 MHz is obtained and

eight master clock periods elapse for every one SCLK period.

Depending on the throughput rate selected, if the timer registers

are loaded with the value, of 803, for example, then 100.5 SCLKs

occur between interrupts and subsequently between transmit

instructions. This situation results in sampling that is not equi-

distant as the transmit instruction is occurring on a SCLK edge.

If the number of SCLKs between interrupts is a whole integer

figure of N, then equidistant sampling is implemented by the DSP.

AD7927 TO DSP563xx

The connection diagram in Figure 31 shows how the AD7927

can be connected to the enhanced synchronous serial interface

(ESSI) of the DSP563xx family of DSPs from Motorola. Each

ESSI (two on board) is operated in synchronous mode (SYN

bit in CRB = 1) with internally generated word length frame

sync for both TX and RX (Bit FSL1 = 0 and Bit FSL0 = 0 in

CRB). Normal operation of the ESSI is selected by making

MOD = 0 in the CRB. Set the word length to 16 by setting bits

WL1 = 1 and WL0 = 0 in CRA. The FSP bit in the CRB should

be set to 1 so the frame sync is negative. It should be noted that

for signal processing applications, it is imperative that the frame

synchronization signal from the DSP563xx provides equidistant

sampling.

In the example shown in Figure 31, the serial clock is taken

from the ESSI so the SCK0 pin must be set as an output, SCKD

= 1. The VDRIVE pin of the AD7927 takes the same supply voltage

as that of the DSP563xx. This allows the ADC to operate at a

higher voltage than the serial interface, that is, DSP563xx, if

necessary.

SCK

SRD

STD

SC2

SCLK

DOUT

DIN

AD7927*

DSP563xx*

VDRIVE

VDD

*ADDITIONAL PINS REMOVED FOR CLARITY.

Figure 31. Interfacing to the DSP563xx

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