Data Sheet

AD7927

Rev. D | Page 13 of 28

SEQUENCER OPERATION

The configuration of the SEQ and SHADOW bits in the control register allows the user to select a particular mode of operation of the

sequencer function. Table 9 outlines the four modes of operation of the sequencer.

Table 9. Sequence Selection

SEQ

SHADOW

Sequence Type

0

0

This configuration means that the sequence function is not used. The analog input channel selected for each

individual conversion is determined by the contents of the channel address bits, ADD0 through ADD2, in each

prior write operation. This mode of operation reflects the traditional operation of a multichannel ADC, without

the sequencer function being used, where each write to the AD7927 selects the next channel for conversion (see

Figure 11).

0

1

This configuration selects the shadow register for programming. The following write operation loads the contents of

the shadow register. This programs the sequence of channels converted on continuously with each successive valid

CS falling edge (see the Shadow Register section, Table 10, and Figure 12). The channels selected need not be

consecutive.

1

0

If the SEQ and SHADOW bits are set in this way, the sequence function is not interrupted upon completion of

the WRITE operation. This allows other bits in the control register to be altered between conversions while in a

sequence, without terminating the cycle.

1

1

This configuration is used in conjunction with the channel address bits, ADD2 to ADD0, to program continuous

conversions on a consecutive sequence of channels from Channel 0 to a selected final channel as determined by

the channel address bits in the control register (see Figure 13).