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TS68040 Datasheet(PDF) 23 Page - ATMEL Corporation |
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TS68040 Datasheet(HTML) 23 Page - ATMEL Corporation |
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23 / 49 page  23 TS68040 2116A–HIREL–09/02 Figure 9. Read/Write Timing Note: Transfer attribute signals UPAN, SIZN, TTN, TMN, TLNN, R/W, LOCK, LOCKE, CIOUT Table 16. JTAG Timing Application (Figure 16 to Figure 19) -55°C ≤T C ≤TJmax; 4.75V ≤VCC ≤5.25V unless otherwise specified (1)(2) Num Characteristic Min Max Unit TCK Frequency 010 MHz 1 TCK Cycle Time 100 ns 2 TCK Clock Pulse Width Measured at 1.5V 40 ns 3 TCK Rise and Fall Times 0 10 ns 4TRST Setup Time to TCK Falling Edge 40 ns 5TRST Assert Time 100 ns 6 Boundary Scan Input Data Setup Time 50 ns 7 Boundary Scan Input Data Hold Time 50 ns 8 TCK to Output Data Valid 0 50 ns 9 TCK to Output High Impedance 0 50 ns 10 TMS, TDI Data Setup Time 20 ns 11 TMS, TDI Data Hold Time 5 ns 12 TCK to TDO Data Valid 0 20 ns 13 TCK to TDO High Impedance 0 20 ns |
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