AD7712 datasheet(16/29 Pages) AD

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REV. F

AD7712

–15–

Antialias Considerations

The digital filter does not provide any rejection at integer mul-

tiples of the modulator sample frequency (n

19.5 kHz, where

n = 1, 2, 3 . . . ). This means that there are frequency bands,

±f

3 dB wide (f3 dB is cutoff frequency selected by FS0 to FS11),

where noise passes unattenuated to the output. However, due to

the AD7712’s high oversampling ratio, these bands occupy only

a small fraction of the spectrum, and most broadband noise is

filtered. In any case, because of the high oversampling ratio, a

simple, RC, single-pole filter is generally sufficient to attenuate

the signals in these bands on the analog input and thus provide

adequate antialiasing filtering.

If passive components are placed in front of the AIN1 input of the

AD7712, care must be taken to ensure that the source impedance

is low enough so as not to introduce gain errors in the system. The

dc input impedance for the AIN1 input is over 1 G

Ω. The input

appears as a dynamic load that varies with the clock frequency

and with the selected gain (see Figure 7). The input sample

rate, as shown in Table III, determines the time allowed for the

analog input capacitor, CIN, to be charged. External impedances

result in a longer charge time for this capacitor, which may result

in gain errors being introduced on the analog inputs. Table IV

shows the allowable external resistance/capacitance values

such that no gain error to the 16-bit level is introduced, while

Table V shows the allowable external resistance/capacitance

values such that no gain error to the 20-bit level is introduced.

Both inputs of the differential input channels (AIN1) look into

similar input circuitry.

RINT

(7k

TYP)

CINT

(11.5pF TYP)

VBIAS

AIN

SWITCHING FREQUENCY DEPENDS ON

fCLKIN AND SELECTED GAIN

HIGH

IMPEDANCE

>1G

Figure 7. AIN1 Input Impedance

Table IV. Typical External Series Resistance That Will Not

Introduce 16-Bit Gain Error

External Capacitance (pF)

Gain

100

500

1000

5000

184 k

Ω 45.3 kΩ 27.1 kΩ 7.3 kΩ 4.1 kΩ 1.1 kΩ

88.6 k

Ω 22.1 kΩ 13.2 kΩ 3.6 kΩ 2.0 kΩ 560 Ω

41.4 k

Ω 10.6 kΩ 6.3 kΩ

1.7 k

Ω 970 Ω

270

Ω

8–128

17.6 k

Ω 4.8 kΩ

2.9 k

Ω

790

Ω

440

Ω

120

Ω

Table V. Typical External Series Resistance That Will Not

Introduce 20-Bit Gain Error

External Capacitance (pF)

Gain

100

500

1000

5000

145 k

Ω 34.5 kΩ 20.4 kΩ 5.2 kΩ 2.8 kΩ 700 Ω

70.5 k

Ω 16.9 kΩ 10 kΩ

2.5 k

Ω 1.4 kΩ 350 Ω

31.8 k

Ω 8.0 kΩ

4.8 k

Ω

1.2 k

Ω 670 Ω

170

Ω

8–128

13.4 k

Ω 3.6 kΩ

2.2 k

Ω

550

Ω

300

Ω

The numbers in Tables IV and V assume a full-scale change on

the analog input. In any case, the error introduced due to longer

charging times is a gain error that can be removed using the

system calibration capabilities of the AD7712 provided that the

resultant span is within the span limits of the system calibration

techniques for the AD7712.

The AIN2 input contains a resistive attenuation network as

outlined in Figure 8. The typical input impedance on this input

is 44 k

Ω. As a result, the AIN2 input should be driven from a

low impedance source.

33k

VBIAS

AIN2

11k

MODULATOR

CIRCUIT

Figure 8. AIN2 Input Impedance

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