REV. A

AD9847

–15–

Bit

Default

Address

Content

Width

Value

Register Name

Register Description

AFE Register Breakdown

Serial Address:

oprmode

[7:0]

8'h0

8'h00 {oprmode[5:0]}, 8'h01 {oprmode[7:6]}

[1:0]

2'h0

powerdown[1:0]

Full Power

2'h1

Fast Recovery

2'h2

Reference Standby

2'h3

Total Shutdown

[2]

disblack

Disable Black Loop Clamping (High Active)

[3]

test mode

Test Mode—Should Be Set Low

[4]

test mode

Test Mode—Should Be Set High

[5]

test mode

Test Mode—Should Be Set Low

[6]

test mode

Test Mode—Should Be Set Low

[7]

test mode

Test Mode—Should Be Set Low

ctlmode

[5:0]

6'h0

Serial Address: 8'h06 {cltmode[5:0]}

[2:0]

3'h0

ctlmode[2:0]

Off

3'h1

Mosaic Separate

3'h2

VD Selected/Mosaic Interlaced

3'h3

Mosaic Repeat

3'h4

Three-Color

3'h5

Three-Color II

3'h6

Four-Color

3'h7

Four-Color II

[3]

enablepxga

Enable PxGA (High Active)

[4]

1'h0

outputlat

Latch Output Data on Selected DOUT Edge

1'h1

Leave Output Latch Transparent

[5]

1'h0

tristateout

ADC Outputs Are Driven

1'h1

ADC Outputs Are Three-Stated

PRECISION TIMING HIGH SPEED TIMING

GENERATION

The AD9847 generates flexible high speed timing signals using

the Precision Timing core. This core is the foundation for generating

the timing used for both the CCD and the AFE, the reset gate RG,

horizontal drivers H1–H4, and the SHP/SHD sample clocks.

A unique architecture makes it routine for the system designer to

optimize image quality by providing precise control over the hori-

zontal CCD readout and the AFE correlated double sampling.

NOTES

1. PIXEL CLOCK PERIOD IS DIVIDED INTO 48 POSITIONS, PROVIDING FINE EDGE RESOLUTION FOR HIGH SPEED CLOCKS.

2. THERE IS A FIXED DELAY FROM THE CLI INPUT TO THE INTERNAL PIXEL PERIOD POSITIONS (

t

P[0]

P[48]=P[0]

P[12]

P[24]

P[36]

1 PIXEL

PERIOD

...

...

CLI

POSITION

Figure 4. High Speed Clock Resolution from CLI Master Clock Input

Timing Resolution

The Precision Timing core uses a 1

master clock input (CLI) as

a reference. This clock should be the same as the CCD pixel clock

frequency. Figure 4 illustrates how the internal timing core

divides the master clock period into 48 steps or edge positions.

Therefore, the edge resolution of the Precision Timing core is

Applications Information section.