AD9847 datasheet(25/28 Pages) AD

25 / 28 page

REV. A

AD9847

–25–

Optical Black Clamp

The optical black clamp loop is used to remove residual offsets in

the signal chain and to track low frequency variations in the CCD’s

black level. During the optical black (shielded) pixel interval on

each line, the ADC output is compared with a fixed black level

reference, selected by the user in the clamp level register. The

value can be programmed between 0 LSB and 63.75 LSB with

8-bit resolution. The resulting error signal is filtered to reduce noise,

and the correction value is applied to the ADC input through a

D/A converter. Normally, the optical black clamp loop is turned

on once per horizontal line, but this loop can be updated more

slowly to suit a particular application. If external digital clamping

is used during the post processing, the AD9847 optical black

clamping may be disabled using Bit D2 in the OPRMODE

still be used to provide programmable offset adjustment.

The CLPOB pulse should be placed during the CCD’s optical

black pixels. It is recommended that the CLPOB pulse duration

be at least 20 pixels wide to minimize clamp noise. Shorter pulse-

widths may be used, but clamp noise may increase, and the

ability to track low frequency variations in the black level will be

reduced. See the section on Horizontal Clamping and Blanking

and also the Applications Information section for timing examples.

A/D Converter

The AD9847 uses a high performance 10-bit ADC architecture,

optimized for high speed and low power. Differential nonlinearity

(DNL) performance is typically better than 0.4 LSB. The ADC

uses a 2 V input range. Better noise performance results from

using a larger ADC full-scale range. See TPC 1 and TPC 2 for

typical linearity and noise performance plots for the AD9847.

APPLICATIONS INFORMATION

External Circuit Configuration

The AD9847 recommended circuit configuration for external

mode is shown in Figure 21. All signals should be carefully

routed on the PCB to maintain low noise performance. The CCD

output signal should be connected to Pin 29 through a 0.1

µF

capacitor. The CCD timing signals H1–H4 and RG should be

routed directly to the CCD with minimum trace lengths, as shown

in Figures 22a and 22b. The digital outputs and clock inputs are

located on Pins 1–12 and Pins 36–44 and should be connected

to the digital ASIC, away from the analog and CCD clock signals.

The CLI signal from the ASIC may be routed under the package

to Pin 23. This will help separate the CLI signal from the H1–H4

and RG signal routing.

Grounding and Decoupling Recommendations

As shown in Figure 21, a single ground plane is recommended

for the AD9847. This ground plane should be as continuous as

possible, particularly around Pins 25 – 35. This will ensure that

all analog decoupling capacitors provide the lowest possible

impedance path between the power and bypass pins and their

respective ground pins. All decoupling capacitors should be located

as close as possible to the package pins. Placing series resistors

close to the digital output pins (Pins 1–12) may help reduce

digital code transition noise. If the digital outputs must drive a

load larger than 20 pF, buffering is recommended to minimize

additional noise.

Power supply decoupling is very important in achieving low noise

performance. Figure 21 shows the local high frequency decoupling

capacitors, but additional capacitance is recommended for lower

frequencies. Additional capacitors and ferrite beads can further

reduce noise.

DIGITAL

SUPPLY

SERIAL

INTERFACE

CCD

SIGNAL

CLOCK

INPUTS

0.1 F

DRIVER

SUPPLY

13 14 15 16

CLOCK

INPUT

17 18 19 20 21 22 23 24

RG DRIVER

SUPPLY

H DRIVER

SUPPLY

ANALOG

SUPPLY

48 47 46 45 44

39 38 37

43 42 41 40

PIN 1

IDENTIFIER

TOP VIEW

(Not to Scale)

REFT

REFB

CMLEVEL

0.1 F

AVSS3

AVDD3

BYP3

(LSB) D0

1 F

DVSS3

1 F

DVDD3

CCDIN

BYP2

BYP1

AVDD2

AD9847

(MSB) D9

AVSS2

ANALOG

SUPPLY

0.1 F

ANALOG

SUPPLY

DATA

OUTPUTS

0.1 F 0.1 F 0.1 F

0.1 F

HIGH-SPEED

CLOCKS

Figure 21. Recommended Circuit Configuration for External Mode

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