REV. A

AD9847

–20–

H-Counter Synchronization

The H-Counter reset occurs on the sixth CLI rising edge following

the HD falling edge. The PxGA steering is synchronized with the

reset of the internal H-Counter (see Figure 13).

POWER-UP PROCEDURE

Recommended Power-Up Sequence

When the AD9847 is powered up, the following sequence is

recommended (refer to Figure 14 for each step).

1. Turn on power supplies for AD9847.

2. Apply the master clock input CLI, VD, and HD.

3. The Precision Timing core must be reset by writing a “0” to the

TGCORE_RSTB Register (Address x026) followed by writ-

ing a “l” to the TGCORE_RSTB Register. This will start the

internal timing core operation. Next, initialize the internal

000

1

12

111

0

03

11

00

01234

5

6

7

89

10

11

12

14

15

01

2

3

02

3

4

H-COUNTER

RESET

VD

NOTES

1. INTERNAL H-COUNTER IS RESET ON THE SIXTH CLI RISING EDGE FOLLOWING THE HD FALLING EDGE.

2. PxGA STEERING IS SYNCHRONIZED WITH THE RESET OF THE INTERNAL H-COUNTER (MOSAIC SEPARATE MODE IS SHOWN).

3. VD FALLING EDGE SHOULD OCCUR ONE CLOCK CYCLE BEFORE HD FALLING EDGE FOR PROPER PxGA LINE SYNCHRONIZATION.

HD

XX

XX

X

X

X

PxGA GAIN

REGISTER

CLI

XX

XX

X

X

X

H-COUNTER

(PIXEL COUNTER)

3ns MIN

23

5

3ns MIN

X

X

Figure 13. H-Counter Synchronization

VDD

(INPUT)

SERIAL

WRITES

VD

(OUTPUT)

1 H

ODD FIELD

EVEN FIELD

DIGITAL

OUTPUTS

CLOCKS ACTIVE WHEN OUT_CONT REGISTER IS

UPDATED AT VD/HD EDGE

H1/H3, RG

H2/H4

CLI

(INPUT)

HD

(OUTPUT)

1V

***

***

***

***

Figure 14. Recommended Power-Up Sequences

circuitry by first writing “110101” or “53” decimal to the

INITIAL1 Register (Address x020). Finally, write “000100”

or “4” decimal to the INITIAL2 Register (Address x00F).

4. Write a “1” to the PREVENTUPDATE Register (Address x019).

This will prevent the updating of the serial register data.

5. Write to the desired registers to configure high speed timing

and horizontal timing.

6. Write a “1” to the OUT_CONT Register (Address x016).

This will allow the outputs to become active after the next

VD/HD rising edge.

7. Write a “0” to the PREVENTUPDATE Register (Address x019).

This will allow the serial information to be updated at the

next VD/HD falling edge.

8. The next VD/HD falling edge allows register updates to occur,

including OUT_CONT, which enables all clock outputs.