REV. A

AD9847

–16–

High Speed Clock Programmability

Figure 5 shows how the high speed clocks RG, H1–H4, SHP,

and SHD are generated. The RG pulse has programmable rising

and falling edges and may be inverted using the polarity control.

The horizontal clocks H1 and H3 have programmable rising and

falling edges and polarity control. The H2 and H4 clocks are

always inverses of H1 and H3, respectively. Table II summarizes

the high speed timing registers and their parameters.

The edge location registers are 6 bits wide, but there are only 48

valid edge locations available. Therefore, the register values are

mapped into four quadrants, with each quadrant containing 12 edge

locations. Table III shows the correct register values for the

corresponding edge locations. Figure 6 shows the range and

default locations of the high speed clock signals.

Table II. H1–H4, RG, SHP, SHD Timing Parameters

Register Name

Length

Range

Description

POL

1b

High/Low

Polarity Control for H1, H3, and RG (0 = No Inversion, 1 = Inversion)

POSLOC

6b

0–47 Edge Location

Positive Edge Location for H1, H3, and RG

Sample Location for SHP, SHD

NEGLOC

6b

0–47 Edge Location

Negative Edge Location for H1, H3, and RG

DRV

3b

0–7 Current Steps

Drive Current for H1–H4 and RG Outputs (3.5 mA per Step)

Table III. Precision Timing Edge Locations

Quadrant

Edge Location (Decimal)

Register Value (Decimal)

Register Value (Binary)

I0 to 11

0 to 11

000000 to 001011

II

12 to 23

16 to 27

010000 to 011011

III

24 to 35

32 to 43

100000 to 101011

IV

36 to 47

48 to 59

110000 to 111011

H1/H3

H2/H4

CCD SIGNAL

RG

(1)

(2)

(3)

(4)

(5)

(6)

NOTES

PROGRAMMABLE CLOCK POSITIONS:

(1) RG RISING EDGE AND (2) FALLING EDGE

(3) SHP AND (4) SHD SAMPLE LOCATION

(5) H1/H3 RISING EDGE POSITION AND (6) FALLING EDGE POSITION (H2/H4 ARE INVERSE OF H1/H3)

Figure 5. High Speed Clock Programmable Locations