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ATSAM2193 Datasheet(PDF) 7 Page - ATMEL Corporation |
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ATSAM2193 Datasheet(HTML) 7 Page - ATMEL Corporation |
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7 / 14 page  7 ATSAM2193/ATSAM2193-G 2695A–DRMSD–06/03 Parallel MPU-401 Interface Timings Figure 3. MPU Interface Read Cycle Figure 4. MPU Interface Write Cycle Table 7. MPU Interface Timing Parameters Symbol Parameter Min Typ Max Unit t AVCS Address valid to chip select low 0 - - ns t CSLRDL Chip select low to RD low 5 - - ns t RDHCSH RD high to CS high 5 - - ns t PRD RD pulse width 50 - - ns t RDLDV Data out valid from RD -- 20 ns t DRH Data out hold from RD 5- 10 ns t CSLRWRL Chip select low to WR low 5 - - ns t WRHCSH WR high to CS high 5 - - ns t PWR WR pulse width 50 - - ns t DWS Write data setup time 10 - - ns t DWH Write data hold time 0 - - ns t WRCYC Write cycle 3 - - µs A0 D0 - D7 tAVCS tCSLRDL tPRD tRDHCSH tRDLDV tDRH CS RD IRQ A0 D0 - D7 tAVCS tCSLWRL tPWR tWRHCSH tDWS tDWH CS WR tWRCYC |
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