DLP650LE datasheet(5/38 Pages) TI1

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DLP650LE

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DLPS095 – NOVEMBER 2017

Product Folder Links: DLP650LE

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Pin Functions (continued)

NET LENGTH

(mils)

SIGNAL

TYPE(1)

DESCRIPTION

NAME

NO.

(2)

Power supply pins required for all DMD operating modes are VSS, VBIAS, VCC, VCCI, VOFFSET, and VRESET.

MICROMIRROR BIAS RESET INPUTS

MBRST(0)

507.20

Non–logic compatible Micromirror Bias

Reset signals. Connected directly to the

array of pixel micromirrors. Used to hold or

release the micromirrors. Bond Pads

connect to an internal pull–down resistor.

MBRST(1)

576.83

MBRST(2)

545.78

MBRST(3)

636.33

MBRST(4)

618.42

MBRST(5)

738.25

MBRST(6)

718.82

MBRST(7)

777.04

MBRST(8)

543.29

MBRST(9)

612.93

MBRST(10)

580.97

MBRST(11)

672.43

MBRST(12)

653.61

MBRST(13)

764.00

MBRST(14)

764.37

MBRST(15)

813.14

SCP CONTROL

SCPCLK

Serial Communications Port Clock. Bond

Pad connects to an internal pulldown circuit.

SCPDI

Serial Communications Port Data. Bond Pad

connects to an internal pulldown circuit.

SCPENZ

Active low serial communications port

enable. Bond pad connects to an internal

pulldown circuit.

SCPDO

Serial communications port output.

OTHER SIGNALS

EVCC

Do Not Connect on the DLP system board.

MODE_A

415.1

Data Bandwidth Mode Select. Bond Pad

connects to an internal pull–down circuit.

Refer to Table 4 for DLP system board

connection information.

PWRDNZ

110.38

Active Low Device Reset. Bond Pad

connects to an internal pull–down circuit.

POWER

VCC

(2)

B11,

B12,

B13,

B16,

R12,

R13,

R16, R17

Power supply for low voltage CMOS logic.

Power supply for normal high voltage at

micromirror address electrodes.

VCCI

(2)

A12,

A14,

A16,

T12,

T14, T16

Power supply for low voltage CMOS LVDS

interface.

VOFFSET

(2)

C1, D1,

M1, N1

Power supply for high voltage CMOS logic.

Power supply for stepped high voltage at

micromirror address electrodes.

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