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DLP650LE Datasheet(PDF) 14 Page - Texas Instruments |
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DLP650LE Datasheet(HTML) 14 Page - Texas Instruments |
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14 / 38 page  VCM VID tr VLVDS max = VCM max + |1/ 2 * VID max Not to Scale | V LVDS min = V CM min ± |1/ 2 * VID max | tf CLOAD Tester channel Device pin output under test 0 VCC Not to Scale tf. tr. Time 14 DLP650LE DLPS095 – NOVEMBER 2017 www.ti.com Product Folder Links: DLP650LE Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Figure 3. SCP Requirements for Rise and Fall Figure 4. Test Load Circuit for Output Propagation Measurement For output timing analysis, the tester pin electronics and its transmission line effects must be taken into account. System designers should use IBIS or other simulation tools to correlate the timing reference load to a system environment. See Figure 4. Figure 5. LVDS Waveform Requirements See Recommended Operating Conditions for VCM, VID, and VLVDS specifications and conditions. |
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