DLP650LE datasheet(12/38 Pages) TI1

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DLP650LE

DLPS095 – NOVEMBER 2017

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(1)

The DMD is designed to conduct absorbed and dissipated heat to the back of the package. The cooling system must be capable of

maintaining the package within the temperature range specified in the Recommended Operating Conditions.

The total heat load on the DMD is largely driven by the incident light absorbed by the active area, although other contributions include

light energy absorbed by the window aperture and electrical power dissipation of the array.

Optical systems should be designed to minimize the light energy falling outside the window clear aperture since any additional thermal

load in this area can significantly degrade the reliability of the device.

6.5 Thermal Information

THERMAL METRIC

DLP650LE

UNIT

FYL Package

149 PINS

Thermal resistance, active area to test point 1 (TP1)(1)

0.50

°C/W

(1)

Applies to LVCMOS pins only. Excludes LVDS pins and test pad pins.

(2)

To prevent excess current, the supply voltage delta |VCCI – VCC| must be less than the specified limit in Recommended Operating

Conditions.

(3)

To prevent excess current, the supply voltage delta |VBIAS – VOFFSET| must be less than the specified limit in Recommended Operating

Conditions.

6.6 Electrical Characteristics

Over operating free-air temperature range (unless otherwise noted).

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VOH

High level output voltage

VCC = 3 V, IOH = – 20 mA

2.4

VOL

Low level output voltage

VCC = 3.6 V, IOL = 15 mA

0.4

IOZ

High impedance output current

VCC = 3.6 V

µA

IIL

Low level input current

VCC = 3.6 V, VI = 0

–60

µA

IIH

High level input current (1)

VCC = 3.6 V, VI = VCC

200

µA

ICC

Supply current VCC (2)

VCC = 3.6 V

479

ICCI

Supply current VCCI (2)

VCCI = 3.6 V

309

IOFFSET

Supply current VOFFSET (3)

VOFFSET = 8.75 V

Supply Input Power Total

3060

6.7 Capacitance at Recommended Operating Conditions

Over operating free-air temperature range, ƒ = 1 MHz (unless otherwise noted).

PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

Input capacitance

Output capacitance

CIM

MBRST(15:0) Input capacitance

1280 × 800 array all inputs interconnected

230

290

DLP650LE Datasheet(PDF) 12 Page - Texas Instruments

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