DLP650LE datasheet(8/38 Pages) TI1

8 / 38 page

DLP650LE

DLPS095 – NOVEMBER 2017

www.ti.com

Product Folder Links: DLP650LE

Submit Documentation Feedback

(1)

Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2)

All voltages are referenced to common ground VSS. VBIAS, VCC, VCCI, VOFFSET, and VRESET power supplies are all required for all DMD

operating modes.

(3)

Exceeding the recommended allowable voltage difference between VCC and VCCI may result in excessive current draw.

(4)

The maximum LVDS input voltage rating applies when each input of a differential pair is at the same voltage potential.

(5)

The highest temperature of the active array (as calculated using Micromirror Array Temperature Calculation) or of any point along the

window edge as defined in Figure 10. The locations of thermal test points TP2, TP3, TP4, and TP5 in Figure 10 are intended to

measure the highest window edge temperature. If a particular application causes another point on the window edge to be at a higher

temperature, then that point should be used.

(6)

Temperature delta is the highest difference between the ceramic test point 1 (TP1) and anywhere on the window edge as shown in

Figure 10. The window test points TP2, TP3, TP4, and TP5 shown in Figure 10 are intended to result in the worst case delta. If a

particular application causes another point on the window edge to result in a larger delta temperature, then that point should be used.

6 Specifications

6.1 Absolute Maximum Ratings

Over operating free-air temperature range (unless otherwise noted).

(1)

MIN

MAX

UNIT

SUPPLY VOLTAGES

VCC

Supply voltage for LVCMOS core logic(2)

–0.5

VCCI

Supply voltage for LVDS Interface (2)

–0.5

VOFFSET

Micromirror Electrode and HVCMOS voltage(2)

–0.5

VMBRST

Input voltage for MBRST(15:0) (2)

–28

|VCCI – VCC|

Supply voltage delta (absolute value)(3)

0.3

INPUT VOLTAGES

Input voltage for all other input pins(2)

–0.5

VCC + 0.3

|VID|

Input differential voltage (absolute value)(4)

700

CLOCKS

ƒCLOCK

Clock frequency for LVDS interface, DCLK_A

400

MHz

ƒCLOCK

Clock frequency for LVDS interface, DCLK_B

400

MHz

ENVIRONMENTAL

TARRAY and TWINDOW

Temperature, operating(5)

°C

Temperature, non–operating(5)

–40

°C

|TDELTA|

Absolute Temperature delta between any point on the window edge and the

ceramic test point TP1(6)

°C

TDP

Dew point temperature, operating and non–operating (noncondensing)

°C

DLP650LE Datasheet(PDF) 8 Page - Texas Instruments

DLP650LE Datasheet(HTML) 8 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38

Datasheet Download

Link URL