SLG46121V datasheet(56/98 Pages) DIALOG

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SLG46121

10.5 Programmable Delay / Edge Detector

The SLG46121 has a programmable time delay logic cell available that can generate a delay that is selectable from one of four

timings (time1) configured in the GreenPAK Designer. The programmable time delay cell can generate one of four different delay

patterns, rising edge detection, falling edge detection, both edge detection and both edge delay. These four patterns can be further

modified with the addition of delayed edge detection, which adds an extra unit of delay as well as glitch rejection during the delay

period. See the timing diagrams below for further information.

Note

: The input signal must be longer than the delay, otherwise it will be filtered out.

10.6 Programmable Delay Timing Diagram - Edge Detector Output

Figure 22. Programmable Delay

Figure 23. Edge Detector Output

Programmable

Delay

OUT

reg <743:742>

From Connection

Matrix Output <58>

To Connection

Matrix Input <29>

reg <745:744>

Edge Mode Selection

Delay Value Selection

reg <746>

Deglitch Filter Out

reg <746>

Deglitch Filter In

time1

Edge Detector

Output

Rising Edge Detector

Falling Edge Detector

Both Edge Detector

Both Edge Delay

time1

time1 can be set by register

SLG46121V Datasheet(PDF) 56 Page - Dialog Semiconductor