SLG46121V datasheet(12/98 Pages) DIALOG

12 / 98 page

000-0046121--106

Page 11 of 97

SLG46121

5.6 Electrical Characteristics (3.3V ±10% VDD2)

Symbol

Parameter

Condition/Note

Min.

Typ.

Max.

Unit

VDD2

Supply Voltage

VDD2 ≤ VDD

1.71

VDD2

ILGK

Input leakage PIN 8, 9, 10, 12

(Absolute Value)

1000

VIH2

HIGH-Level Input Voltage

PIN 8, 9, 10, 12

Logic Input, VDD2 = 1.8 V

1.100

VDD2

Logic Input with Schmitt Trigger,

VDD2 = 1.8 V

1.270

VDD2

Low-Level Logic Input, VDD2 = 1.8 V

0.980

VDD2

VIL2

LOW-Level Input Voltage

PIN 8, 9, 10, 12

Logic Input, VDD2 = 1.8 V

0.690

Logic Input with Schmitt Trigger,

VDD2 = 1.8 V

0.440

Low-Level Logic Input, VDD2 = 1.8 V

0.520

VOH2

HIGH-Level Output Voltage

PIN 8, 9, 10, 12

Push-Pull 1X, Open Drain PMOS 1X,

IOH = 100 A, VDD2 = 1.8 V

1.680

1.790

Push-Pull 2X, Open Drain PMOS 2X,

IOH = 100 A, VDD2 = 1.8 V

1.700

1.800

VOL2

LOW-Level Output Voltage

PIN 8, 9, 10, 12

Push-Pull 1X,

IOL= 100 A, VDD2 = 1.8 V

0.020

0.030

Push-Pull 2X,

IOL= 100 A, VDD2 = 1.8 V

0.010

0.020

Open Drain NMOS 1X,

IOL= 100 A, VDD2 = 1.8 V

0.010

0.020

Open Drain NMOS 2X,

IOL= 100 A, VDD2 = 1.8 V

0.010

IOH2

HIGH-Level Output Current

(see Note 1)

PIN 8, 9, 10, 12

Push-Pull 1X, Open Drain PMOS 1X,

VOH = VDD - 0.2, VDD2 = 1.8 V

1.000

1.390

Push-Pull 2X, Open Drain PMOS 2X,

VOH = VDD - 0.2, VDD2 = 1.8 V

2.100

2.680

IOL2

LOW-Level Output Current

(see Note 1)

PIN 8, 9, 10, 12

Push-Pull 1X,

VOL = 0.15 V, VDD2 = 1.8 V

0.760

1.340

Push-Pull 2X,

VOL = 0.15 V, VDD2 = 1.8 V

1.520

2.660

Open Drain NMOS 1X,

VOL = 0.15 V, VDD2 = 1.8 V

1.530

2.670

Open Drain NMOS 2X,

VOL = 0.15 V, VDD2 = 1.8 V

3.060

5.136

IVDD2

Maximum Average or DC

Current Through VDD2 Pin

(Per chip side, see Note 2)

TJ = 85°C

TJ = 110°C

IGND

Maximum Average or DC

Current Through GND Pin

(Per chip side, see Note 2)

TJ = 85°C

TJ = 110°C

Note 1: DC or average current through any pin should not exceed value given in Absolute Maximum Conditions.

Note 2: The GreenPAK’s power rails are divided in two sides. Pins 2, 3, 4, 5 and 6 are connected to one side, pins 8, 9, 10 and

12 to another.

SLG46121V Datasheet(PDF) 12 Page - Dialog Semiconductor

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