SLG46121V datasheet(71/98 Pages) DIALOG

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000-0046121--106

Page 70 of 97

SLG46121

12.1 CNT/DLY0 Register Settings

Figure 44. CNT/DLY1

Table 53. CNT/DLY0 Register Settings

Signal Function

Address

Counter/Delay0

Mode Select

reg <548>

0: Delay Mode

1: Counter Mode

Counter/Delay0

Clock Source Select

(external clock is

only for counter

mode)

reg <551:549>

000: Internal OSC Clock

001: OSC/4

010: OSC/12

011: OSC/24

100: OSC/64

101: External Clock

110: Reserved

111: Reserved

Counter0 Control

Data/Delay0 Time

Control

reg <565:552>

1-16383: (delay time = (counter control data +2) /freq)

Delay0 Mode Select

or asynchronous

counter reset

reg <567:566>

00: Delay on both falling and rising edges

01: Delay on falling edge only

10: Delay on rising edge only

11: No delay on either falling or rising edges

CNT/DLY1

Counter_end

clk

To Connection

Matrix Input <24>

From Connection

Matrix Output <54>

Count_end_out_x-1

reg <568>

ext. clock from CM Out<53>

RC Osc/64

RC Osc/24

RC Osc/12

RC Osc/4

RC Osc

Counter Control Data

reg <579:572>

reg <571:569>

Delay_out

Delay_IN

Reset_IN

Edge Detector

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