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TMS320F28062 Datasheet(PDF) 39 Page - Texas Instruments |
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TMS320F28062 Datasheet(HTML) 39 Page - Texas Instruments |
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39 / 179 page ![]() 39 TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.com SPRS698F – NOVEMBER 2010 – REVISED MARCH 2016 Submit Documentation Feedback Product Folder Links: TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 Detailed Description Copyright © 2010–2016, Texas Instruments Incorporated (1) IEEE Standard 1149.1-1990 Standard Test Access Port and Boundary Scan Architecture 6.1.5 Peripheral Bus To enable migration of peripherals between various Texas Instruments (TI) MCU family of devices, the devices adopt a peripheral bus standard for peripheral interconnect. The peripheral bus bridge multiplexes the various busses that make up the processor Memory Bus into a single bus consisting of 16 address lines and 16 or 32 data lines and associated control signals. Three versions of the peripheral bus are supported. One version supports only 16-bit accesses (called peripheral frame 2). Another version supports both 16- and 32-bit accesses (called peripheral frame 1). 6.1.6 Real-Time JTAG and Analysis The devices implement the standard IEEE 1149.1 JTAG (1) interface for in-circuit based debug. Additionally, the devices support real-time mode of operation allowing modification of the contents of memory, peripheral, and register locations while the processor is running and executing code and servicing interrupts. The user can also single step through non-time-critical code while enabling time- critical interrupts to be serviced without interference. The device implements the real-time mode in hardware within the CPU. This is a feature unique to the 28x family of devices, requiring no software monitor. Additionally, special analysis hardware is provided that allows setting of hardware breakpoint or data/address watch-points and generating various user-selectable break events when a match occurs. 6.1.7 Flash The F28069, F28068, F28067, and F28066 devices contain 128K × 16 of embedded flash memory, segregated into eight 16K × 16 sectors. The F28065, F28064, F28063, and F28062 devices contain 64K × 16 of embedded flash memory, segregated into eight 8K × 16 sectors. All devices also contain a single 1K × 16 of OTP memory at address range 0x3D 7800 – 0x3D 7BF9. The user can individually erase, program, and validate a flash sector while leaving other sectors untouched. However, it is not possible to use one sector of the flash or the OTP to execute flash algorithms that erase or program other sectors. Special memory pipelining is provided to enable the flash module to achieve higher performance. The flash/OTP is mapped to both program and data space; therefore, it can be used to execute code or store data information. Addresses 0x3F 7FF0 – 0x3F 7FF5 are reserved for data variables and should not contain program code. NOTE The Flash and OTP wait-states can be configured by the application. This allows applications running at slower frequencies to configure the flash to use fewer wait-states. Flash effective performance can be improved by enabling the flash pipeline mode in the Flash options register. With this mode enabled, effective performance of linear code execution will be much faster than the raw performance indicated by the wait-state configuration alone. The exact performance gain when using the Flash pipeline mode is application-dependent. For more information on the Flash options, Flash wait-state, and OTP wait-state registers, see the Systems Control and Interrupts chapter of the TMS320x2806x Piccolo Technical Reference Manual (SPRUH18). |
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