TMS320F28062 datasheet(72/179 Pages) TI1

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WDCLK

WDCR (WDPS[2:0])

WDCLK

WDCNTR(7:0)

WDKEY(7:0)

Good Key

WDCR (WDCHK[2:0])

Bad

WDCHK

Key

WDCR (WDDIS)

Clear Counter

SCSR (WDENINT)

Watchdog

Prescaler

Generate

Output Pulse

(512 OSCCLKs)

8-Bit

Watchdog

Counter

CLR

WDRST

WDINT

Watchdog

55 + AA

Key Detector

XRS

Core-reset

WDRST(A)

Internal

Pullup

TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066

TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062

SPRS698F – NOVEMBER 2010 – REVISED MARCH 2016

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Product Folder Links: TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065

TMS320F28064 TMS320F28063 TMS320F28062

Detailed Description

Normally, when the input clocks are present, the CPU-watchdog counter decrements to initiate a CPU-

watchdog reset or WDINT interrupt. However, when the external input clock fails, the CPU-watchdog

counter stops decrementing (that is, the watchdog counter does not change with the limp-mode clock).

NOTE

The CPU-watchdog is different from the NMI watchdog. The CPU-watchdog is the legacy

watchdog that is present in all 28x devices.

NOTE

Applications in which the correct CPU operating frequency is absolutely critical should

implement a mechanism by which the MCU will be held in reset, should the input clocks ever

fail. For example, an R-C circuit may be used to trigger the XRS pin of the MCU, should the

capacitor ever get fully charged. An I/O pin may be used to discharge the capacitor on a

periodic basis to prevent it from getting fully charged. Such a circuit would also help in

detecting failure of the flash memory.

The WDRST signal is driven low for 512 OSCCLK cycles.

Figure 6-15. CPU-Watchdog Module

The WDINT signal enables the watchdog to be used as a wakeup from IDLE/STANDBY mode.

In STANDBY mode, all peripherals are turned off on the device. The only peripheral that remains

functional is the CPU-watchdog. This module will run off OSCCLK. The WDINT signal is fed to the LPM

block so that it can wake the device from STANDBY (if enabled). See Section 6.7 for more details.

In IDLE mode, the WDINT signal can generate an interrupt to the CPU, through the PIE, to take the CPU

out of IDLE mode.

In HALT mode, the CPU-watchdog can be used to wake up the device through a device reset.

TMS320F28062 Datasheet(PDF) 72 Page - Texas Instruments

TMS320F28062 Datasheet(HTML) 72 Page - Texas Instruments

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