AD9675KBCZ datasheet(33/61 Pages) AD

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AD9675

Data Sheet

Rev. A | Page 32 of 60

Table 17. JESD204B Configurable Identification Values

DID Value

Value Range

LID (SERDOUT1±)

0x148, [4:0]

0 to 31

LID (SERDOUT2±)

0x149, [4:0]

0 to 31

LID (SERDOUT3±)

0x14A, [4:0]

0 to 31

LID (SERDOUT4±)

0x14B, [4:0]

0 to 31

DID

0x146, [7:0]

0 to 255

BID

0x147, [3:0]

0 to 15

Set Number of Frames per Multiframe, K

Per the JESD204B specification, a multiframe is defined as a group

of K successive frames, where K is between 1 and 32, and it

requires that the number of octets be between 17 and 1024. The

K value is set to 32 by default in Register 0x152, Bits[4:0]. Note

that Register 0x152 represents a value of K − 1.

The K value can be changed; however, it must comply with a

few conditions. The AD9675 uses a fixed value for octets per

frame, F. K must also be a multiple of 4 and conform to the

following equation:

32 ≥ K ≥ Ceil(17/F)

The JESD204B specification also requires that the number of

octets per multiframe (K × F) be between 17 and 1024. The F

value is fixed based on the value of M and L. F can be read from

Address 0x151.





Enable Scramble, SCR

Scrambling can be enabled or disabled by setting Address 0x150,

Bit 7. By default, scrambling is enabled. Per the JESD204B

protocol, scrambling is only functional after the lane

synchronization is complete.

Set Lane Synchronization Options

Most of the synchronization features of the JESD204B interface

are enabled by default for typical applications. In some cases,

these features can be disabled or modified as follows.

ILAS enabling is controlled in Address 0x142, Bits[3:2] and is

enabled by default. Optionally, to support some unique

instances of the interfaces (such as NMCDA-SL), the JESD204B

interface can be programmed to either disable the ILAS

sequence or continually repeat the ILAS sequence. Additionally,

the ILAS can be repeated for a fixed count, as programmed in

Address 0x145, Bits[7:0].

The AD9675 has fixed values of some of the JESD204B interface

parameters, and they are as follows:



N' = 16: number of bits per sample is 16. Read only value

from Address 0x155, Bits[3:0] = 15 (N' − 1).



CF = 0: number of control words per frame clock cycle per

converter is 0, in Address 0x157, Bits[4:0].

The AD9675 calculates values for some JESD204B parameters

based on other settings, particularly the quick configuration

the register map for verification:



F: octets per frame can be 32, 16, 8, or 4; read the value

(F − 1) from Address 0x151, Bits[4:0]



M: number of converters per link can be 8 or 16; read the

value (M − 1) from Address 0x153, Bits[3:0]



S: samples per converter per frame is 1; read the value

(S − 1) from Address 0x156, Bit 0.

Check FCHK, Checksum of JESD204B Interface

Parameters

The JESD204B parameters can be verified through a checksum

value (FCHK) of the JESD204B interface parameters. Each lane

has a FCHK value associated with it. The FCHK value is

transmitted during the ILAS second multiframe and can be

read from the internal registers.

Checksum value is the modulo 256 sum of the parameters listed

as Octet 0 to Octet 10 in Table 18. Checksum is calculated by

adding the parameter fields before they are packed into the octets.

The FCHK for the lane configuration for data coming out of

SERDOUT1± can be read from Address 0x15A. Similarly,

FCHK for the lane defined for SERDOUT2± can be read from

Address 0x15B.

Table 18. JESD204B Configuration Table Used in ILAS and

Checksum Calculation

No.

Bit 7

(MSB)

Bit

Bit 0

(LSB)

DID[7:0]

BID[3:0]

LID[4:0]

SCR

L[4:0]

F[7:0]

K[4:0]

M[7:0]

CS[1:0]

N[4:0]

N'[4:0]

S[4:0]

CF[4:0]

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