AD9675KBCZ datasheet(37/61 Pages) AD

37 / 61 page

AD9675

Data Sheet

Rev. A | Page 36 of 60

Additional SPI options allow the user to further increase the

output driver voltage swing of all four outputs to drive longer

trace lengths (see Address 0x015 in Table 31). Even though this

produces sharper rise and fall times on the data edges and is less

prone to bit errors, the power dissipation of the DRVDD supply

increases when this option is used. See the Memory Map section

for more details.

Preemphasis

Preemphasis enables the receiver eye diagram mask to be met

in conditions where the interconnect insertion loss is not in

accordance with the JESD204B specification. In conditions

where pre-emphasis is not needed to achieve sufficient signal

integrity for the link, it is best to disable the pre-emphasis to

conserve power. Enabling pre-emphasis on a short link and

increasing the de-emphasis value too high may cause the

receiver eye diagram to fail in cases where it passes with no de-

emphasis. The transmitter eye diagram does not necessarily

pass when pre-emphasis is enabled. Furthermore, using more

pre-emphasis than necessary may increase EMI; therefore,

consider EMI when choosing an insertion loss compensation

strategy. To enable pre-emphasis, write a Logic 1 to

Address 0x015, Bit 1.

There are several methods to select test data patterns on the

JESD204B link, as shown in Figure 55. These methods serve

different purposes in the testing process of establishing the link.

The processed samples from the ADC can be replaced by nine

digital output test pattern options. The replacement is initiated

through the SPI using Address 0x00D, Bits[3:0]. These options

are useful when validating receiver capture and timing. See

Table 21 for the output test mode bit sequencing options. Some

test patterns have two serial sequential words, which the user

can alternate in various ways, depending on the test pattern

chosen. Note that some patterns may not adhere to the data

format select option. In addition, custom user defined test

patterns are assigned in the user pattern registers (Address 0x019

through Address 0x020). All test mode options except PN

sequence short and PN sequence long can support 8-bit to 14-bit

word lengths to verify data capture to the receiver.

The PN sequence short pattern produces a pseudorandom bit

sequence that repeats itself every 29 − 1 bits, or 511 bits. For a

description of the PN sequence short pattern and how it is

generated, see Section 5.1 of the ITU-T O.150 (05/96) standard.

The only difference from the standard is that the starting value

is a specific value instead of all 1s (see Table 20 for the initial

values).

The PN sequence long pattern produces a pseudorandom bit

sequence that repeats itself every 223 − 1 bits, or 8,388,607 bits.

For a description of the PN sequence long pattern and how it is

generated, see Section 5.6 of the ITU-T O.150 (05/96) standard.

The only differences from the standard are that the starting

value is a specific value instead of all 1s and that the AD9675

inverts the bit stream with relation to the ITU-T standard (see

Table 20 for the initial values). The output sample size depends on

the selected bit length.

Table 20. PN Sequence Initial Values

Sequence

Initial

Value

First Three Output Samples

(MSB First, 16-Bit)

PN Sequence Short

0x092

0x496F, 0xC9A9, 0x980C

PN Sequence Long

0x003

0xFF5C, 0x0029, 0xB80A

See the Memory Map section for information on how to change

these additional digital output timing features through the SPI.

Test patterns are initiated at the input of the scrambler block by

setting Address 0x144, Bits[5:4] = 10 or at the output of the 8-bit/

10-bit encoder by setting Address 0x144, Bits[5:4] = 01. The test

pattern generated is selected in Address 0x144, Bits[3:0], and is

specified in Table 22.

AD9675KBCZ Datasheet(PDF) 37 Page - Analog Devices

AD9675KBCZ Datasheet(HTML) 37 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61

Datasheet Download

Link URL