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AD9675KBCZ Datasheet(PDF) 55 Page - Analog Devices |
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AD9675KBCZ Datasheet(HTML) 55 Page - Analog Devices |
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55 / 61 page  AD9675 Data Sheet Rev. A | Page 54 of 60 Addr. (Hex) Register Name Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) Default Value Comments 0x11E RESERVED_ 11E 0 0 0 0 0 0 0 0 0x00 Reserved 0x11F RESERVED_ 11F 0 0 0 0 0 0 0 0 0x00 Reserved 0x120 CW_ TEST_ TONE 0 CW I/Q output swap 0 = disable (default) 1 = enable LNA offset cancella- tion 0 = enable (default) 1 = disable LNA offset cancellation transconductance 00 = 0.5 mS (default) 01 = 1.0 mS 10 = 1.5 mS 11 = 2.0 mS CW analog test tone override for Address 0x116, Bits [1:0] 00 = disable override (default) 01 = set analog test tone frequency to fLO 1X = set analog test tone frequency to dc 0 0x00 Sets the frequency of the analog test tone to fLO in CW Doppler mode; enables I/Q output swap; LNA offset cancellation control (global) 0x142 JTX_ LINK_ CTRL1 JESD204B power during standby 0 = remain powered up (default) 1 = power down JESD204B tail bit value 0 = zeros (default) 1 = PN sequence JESD204B test mode enable 0 = disable (default) 1 = enable JESD204 B lane sync enable 0 = disable (default) 1 = enable JESD204B ILAS enable 00 = disable (default) 01 = enable 10 = always on, test mode 11 = reserved JESD204B serial frame alignment character insertion (FACI) disable 0: FACI enabled 1: FACI disabled Power down JESD204B link 0 = link enabled (default) 1 = link powered down 0x00 JESD204B configuration (global) 0x143 JTX_ LINK_ CTRL2 SYNCINB signal polarity 0 = not inverted (default) 1 = inverted 0 0 8-bit/ 10-bit encoder 0 = enable (default) 1 = bypass (test mode only) 10-bit transmit bit invert 0 = not inverted (default) 1 = inverted SERD- OUTx± 10-bit transmit bit mirror 0 = not mirrored (default) 1 = mirrored 0x00 JESD204B configuration (global) 0x144 JTX_ LINK_ CTRL3 Checksum enable 0 = enable (default) 1 = disable Checksum algorithm 0 = add parameter (default) 1 = add packed octets JESD204B test pattern input selection 00 = reserved (default) 01 = 10-bit test data injected at output of 8-bit/10-bitencoder 10 = 8-bit test data injected at input of scrambler 11 = reserved JESD204B test mode selection 0000 = off (default) 0001 = alternating checkerboard 0010 = 1-/0-word toggle 0011 = PN sequence long 0100 = PN sequence short 0101 = continuous/repeat user test pattern 0110 = single user test pattern 0111 = ramp output 1000 = RPAT sequence 1001 = reserved … 1111 = reserved 0x00 JESD204B test mode and checksum controls (global) 0x145 JTX_ LINK_ CTRL4 Initial lane alignment sequence repeat count 0000 0000 = 4 × K + 1 (default) 0000 0001 = 4 × K + 2 … 1111 1111 = 4 × K + 128 0x00 JESD204B ILAS repeat count (global) 0x146 JTX_DID_ CFG JESD204B serial device identification (DID) number 0x00 Global 0x147 JTX_BID_ CFG X X X X JESD204B serial bank identification (BID) number (extension to DID) 0x00 Global 0x148 JTX_LID0_ CFG X X X Serial lane identification (LID) number for Lane 1 0x00 Global 0x149 JTX_LID1_ CFG X X X Serial lane identification (LID) number for Lane 2 0x01 Global |
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