X4643 datasheet(12/22 Pages) XICOR

12 / 22 page

X4643/5 – Preliminary Information

Characteristics subject to change without notice.

12 of 22

REV 1.26 4/30/02

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There is a similar operation, called “Set Current

Address” where the device does no operation, but

enters a new address into the address counter if a stop

is issued instead of the second start shown in Figure

13. The device goes into standby mode after the stop

and all bus activity will be ignored until a start is

detected. The next Current Address Read operation

reads from the newly loaded address. This operation

could be useful if the master knows the next address it

needs to read, but is not ready for the data.

Sequential Read

Sequential reads can be initiated as either a current

address read or random address read. The ﬁrst Data

Byte is transmitted as with the other modes; however,

the master now responds with an acknowledge, indi-

cating it requires additional data. The device continues

to output data for each acknowledge received. The

master terminates the read operation by not respond-

ing with an acknowledge and then issuing a stop con-

dition.

The data output is sequential, with the data from

address n followed by the data from address n + 1. The

address counter for read operations increments

through all page and column addresses, allowing the

entire memory contents to be serially read during one

operation. At the end of the address space the counter

“rolls over” to address 0000H and the device continues

to output data for each acknowledge received. Refer to

Figure 14 for the acknowledge and data transfer

sequence.

Figure 14. Sequential Read Sequence

Data

(2)

Slave

Address

Data

(n)

SDA Bus

Signals from

the Slave

Signals from

the Master

Data

(n-1)

(n is any integer greater than 1)

Data

(1)

X4643/5 Addressing

SLAVE ADDRESS BYTE

Following a start condition, the master must output a

Slave Address Byte. This byte consists of several parts:

– a device type identiﬁer that is ‘1010’ to access the

array

– one bits of ‘0’.

– next two bits are the device address.

– one bit of the slave command byte is a R/W bit. The

R/W bit of the Slave Address Byte deﬁnes the opera-

tion to be performed. When the R/W bit is a one, then

a read operation is selected. A zero selects a write

operation. Refer to Figure 15.

– After loading the entire Slave Address Byte from the

SDA bus, the device compares the input slave byte

data to the proper slave byte. Upon a correct com-

pare, the device outputs an acknowledge on the SDA

line.

Word Address

The word address is either supplied by the master or

obtained from an internal counter. The internal counter

is undeﬁned on a power up condition.

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