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HT66F019 Datasheet(PDF) 106 Page - Holtek Semiconductor Inc |
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HT66F019 Datasheet(HTML) 106 Page - Holtek Semiconductor Inc |
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106 / 175 page  Rev. 1.00 106 De�e��e� 01� �01� Rev. 1.00 10� De�e��e� 01� �01� HT66F019 A/D Flash MCU with EEPROM HT66F019 A/D Flash MCU with EEPROM Bit4 ACE4:DefinePA5isA/Dinputornot 0:NotA/Dinput 1:A/Dinput,AN4 Bit3 ACE3:DefinePA4isA/Dinputornot 0:NotA/Dinput 1:A/Dinput,AN3 Bit2 ACE2:DefinePB2isA/Dinputornot 0:NotA/Dinput 1:A/Dinput,AN2 Bit1 ACE1:DefinePB1isA/Dinputornot 0:NotA/Dinput 1:A/Dinput,AN1 Bit0 ACE0:DefinePB0isA/Dinputornot 0:NotA/Dinput 1:A/Dinput,AN0 A/D Converter Operation TheSTARTbitintheSADC0registerisusedtostarttheA/Dconversion.Whenthemicrocontroller setsthisbitfromlowtohighandthenlowagain,ananalogtodigitalconversioncyclewillbeinitiated. TheADBZbitintheSADC0registerisusedtoindicatewhethertheanalogtodigitalconversion processisinprogressornot.Thisbitwillbeautomaticallysetto1bythemicrocontrollerafteran A/Dconversionissuccessfullyinitiated.WhentheA/Dconversioniscomplete,theADBZwillbe clearedto0.Inaddition,thecorrespondingA/Dinterruptrequestflagwillbesetintheinterrupt controlregister,andiftheinterruptsareenabled,anappropriateinternalinterruptsignalwillbe generated.ThisA/DinternalinterruptsignalwilldirecttheprogramflowtotheassociatedA/D internalinterruptaddressforprocessing.IftheA/Dinternalinterruptisdisabled,themicrocontroller canpolltheADBZbitintheSADC0registertocheckwhetherithasbeenclearedasanalternative methodofdetectingtheendofanA/Dconversioncycle. TheclocksourcefortheA/Dconverter,whichoriginatesfromthesystemclockfSYS,canbechosen tobeeitherfSYSorasubdividedversionoffSYS.Thedivisionratiovalueisdeterminedbythe SACKS2~SACKS0bitsintheSADC1register.AlthoughtheA/Dclocksourceisdeterminedby thesystemclockfSYSandbybitsSACKS2~SACKS0,therearesomelimitationsonthemaximum A/Dclocksourcespeedthatcanbeselected.AstherecommendedrangeofpermissibleA/Dclock period,tADCK,isfrom0.5μsto10μs,caremustbetakenforsystemclockfrequencies.Forexample, asthesystemclockoperatesatafrequencyof8MHz,theSACKS2~SACKS0bitsshouldnotbeset to000,001or111.DoingsowillgiveA/Dclockperiodsthatarelessthantheminimumorlarger thanthemaximumA/DclockperiodwhichmayresultininaccurateA/Dconversionvalues.Refer tothefollowingtableforexamples,wherevaluesmarkedwithanasterisk*showwhere,depending uponthedevice,specialcaremustbetaken,asthevaluesmaybelessorlargerthanthespecifiedA/D ClockPeriodrange. fSYS A/D Clock Period (tADCK) SACKS[2:0] = 000 (fSYS) SACKS[2:0] = 001 (fSYS/2) SACKS[2:0] = 010 (fSYS/4) SACKS[2:0] = 011 (fSYS/8) SACKS[2:0] = 100 (fSYS/16) SACKS[2:0] = 101 (fSYS/32) SACKS[2:0] = 110 (fSYS/64) SACKS[2:0] = 111 (fSYS/128) 1MHz 1μs 2μs 4μs 8μs 16μs * 32μs * 64μs * 128μs * �MHz 500ns 1μs 2μs 4μs 8μs 16μs * 32μs * 64μs * 4MHz �50ns * 500ns 1μs 2μs 4μs 8μs 16μs * 32μs * 8MHz 1�5ns * �50ns * 500ns 1μs 2μs 4μs 8μs 16μs * 1�MHz 83ns* 16�ns* 333ns* 66�ns 1.33μs 2.67μs 5.33μs 10.67μs* 16MHz 6�.5ns* 1�5ns* �50ns* 500ns 1μs 2μs 4μs 8μs A/D Clock Period Examples |
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