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AD5255 Datasheet(PDF) 12 Page - Analog Devices

Part # AD5255
Description  3-Channel Digital Potentiometer with Nonvolatile Memory
PDF  20 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD5255 Datasheet(HTML) 12 Page - Analog Devices

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AD5255
Rev. 0 | Page 12 of 20
A random read operation is shown in Figure 21. This operation
changes the address counter to the specified memory address by
performing a dummy write and then performing a read
operation beginning at the new address counter location.
EEPROM Write Protection
Setting the WP pin to a logic low protects the EEPROM
memory from future write operations. In this mode, EEPROM
read operations and RDAC register loading operate normally.
RDAC I2C INTERFACE
DATA
DATA
SA
A
A
A
A
10
0
0
1
R
EE/
RD
A
4
A
3
A
2
A
1
A
0
AC
CMD/
REG
R
1
10
0
P
0 WRITE
(N BYTES + ACKNOWLEDGE)
RDAC ADDRESS
RDAC SLAVE ADDRESS
A/A
Figure 22. RDAC Write
SA
A
A
11
0
1
R
A
RDAC EEPROM OR REGISTER DATA
RDAC EEPROM OR REGISTER DATA
R
1
10
0
P
1 READ
(N BYTES + ACKNOWLEDGE)
RDAC SLAVE ADDRESS
A
Figure 23. RDAC Current Read
SLAVE ADDRESS
RDAC ADDRESS
S
0 WRITE
AA
P
W
SLAVE ADDRESS
RDAC DATA
SR
1 READ
REPEATED START
A
(N BYTES + ACKNOWLEDGE)
A/A
Figure 24. RDAC Random Read
SA
A
A
10
0
1
R
C
1
C
2
C
3
C
0
A
2
A
1
A
0
CMD/
REG
R
1
10
0
P
A
0 WRITE
1 CMD
RDAC SLAVE ADDRESS
Figure 25. RDAC Shortcut Command
Table 5. RDAC Register Addresses (CMD/REG = 0, EE/RDAC = 0)
A4
A3
A2
A1
A0
RDAC
Byte Description
0
0
0
0
0
RDAC0
(D7)(D6)(D5)(D4)(D3)(D2)(D1)(D0) – RDAC0 8 LSBs
0
0
0
0
1
RDAC0
(X)(X)(X)(X)(X)(X)(X)(D8) – RDAC0 MSB
0
0
0
1
0
RDAC1
(D7)(D6)(D5)(D4)(D3)(D2)(D1)(D0) – RDAC1 8 LSBs
0
0
0
1
1
RDAC1
(X)(X)(X)(X)(X)(X)(X)(D8) – RDAC1 MSB
0
0
1
0
0
RDAC2
(X)(D6)(D5)(D4)(D3)(D2)(D1)(D0) – RDAC2 7 bits
0
0
1
0
1
Reserved
…to…
1
1
1
1
1



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